[coreboot-gerrit] Change in coreboot[master]: nb/intel/ironlake: Account for TSEG alignment

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45920 )

Change subject: nb/intel/ironlake: Account for TSEG alignment
......................................................................

nb/intel/ironlake: Account for TSEG alignment

The TSEGMB register has 1 MiB granularity, but do not rely on reserved
bits being zero. Raminit aligns TSEG to a 8 MiB boundary, anyway.

Change-Id: Iedb63f7c7a29172da187030e33197fc6e4ee23f8
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/ironlake/memmap.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/45920/1

diff --git a/src/northbridge/intel/ironlake/memmap.c b/src/northbridge/intel/ironlake/memmap.c
index 78fbae8..221ae92 100644
--- a/src/northbridge/intel/ironlake/memmap.c
+++ b/src/northbridge/intel/ironlake/memmap.c
@@ -14,7 +14,7 @@
 static uintptr_t northbridge_get_tseg_base(void)
 {
    /* Base of TSEG is top of usable DRAM */
-	return pci_read_config32(PCI_DEV(0, 0, 0), TSEG);
+	return ALIGN_DOWN(pci_read_config32(PCI_DEV(0, 0, 0), TSEG), 1 * MiB);
 }

static size_t northbridge_get_tseg_size(void)