[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/denverton_ns: Implement PCIe post config + lock

[Steve Mooney (Code Review)]

Steve Mooney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25442 )

Change subject: soc/intel/denverton_ns: Implement PCIe post config + lock
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Patch Set 14: Code-Review-1

(1 comment)

One bug to fix.  The rest looks good.

https://review.coreboot.org/#/c/25442/14/src/soc/intel/denverton_ns/lpc.c 
File src/soc/intel/denverton_ns/lpc.c:

https://review.coreboot.org/#/c/25442/14/src/soc/intel/denverton_ns/lpc.c@39... 
PS14, Line 392: 			dev = dev_find_slot(0, PCI_DEVFN(PCIE_PORT2_DEV + i,
Should be PCIE_PORT5_DEV