Attention is currently required from: Nico Huber, Paul Menzel, Arthur Heymans, Michael Niewöhner, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52110 )
Change subject: mb/hp/280_g2/romstage.c: Correct CaVrefConfig setting ......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52110/comment/c943dd2b_d91b799a PS1, Line 9: With DDR4, CA Vref goes to channel 0, and CH1 Vref goes to channel 1.
Sorry, I do not fully grasp the explanation. […]
From the KabylakeFspBinPkg FspmUpd.h header:
/** Offset 0x0093 - VREF_CA CA Vref routing: board-dependent 0: VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B, 2: VREF_CA to CH_A and VREF_DQ_B to CH_B **/ UINT8 CaVrefConfig;
The Skylake memory controller has two channels and three Vref circuits: VREF_DQ_A, VREF_DQ_B, VREF_CA. CH_A and CH_B are channel 0 and channel 1, respectively.
Generally, boards using DDR3 or LPDDR3 use the VREF_DQ_A and VREF_DQ_B circuits to control write Vref on channel 0 and channel 1, respectively. The VREF_CA circuit is used to control CA Vref for both channels. This corresponds to FSP setting 0.
With DDR4, write Vref is configured through Mode Register 6 of the DRAM, so the VREF_DQ_A and VREF_DQ_B circuits are no longer used for write Vref. It is thus possible to repurpose one of the VREF_DQ circuits in order to have per-channel control of CA Vref.
About DDR4, the SKL-S PDG (Platform Design Guide) recommends using the VREF_CA circuit to control CA Vref on channel 0, and the VREF_DQ_B circuit to control CA Vref on channel 1. This is to simplify routing the Vref signal from the processor to the DRAM, which eases the task of mainboard designers. This corresponds to FSP setting 2.
However, one of the Skylake RVPs (Reference Validation Platforms) uses the VREF_DQ_A circuit to control CA Vref on channel 1 (I guess Intel engineers then realized that using the VREF_DQ_B circuit eases routing the traces on the mainboard). This corresponds to FSP setting 1.
This picture of the HP 280 G2 schematics shows which Vref circuits are used: https://imgur.com/Bn5g5ps.png
On the left side, the DDR_VREF_CA pin corresponds to the VREF_CA circuit, and is wired to channel 0 (not shown). On the right side, the SA_DIMM_VREFDQ and SB_DIMM_VREFDQ pins correspond to the VREF_DQ_A and VREF_DQ_A circuits, respectively. Note how SA_DIMM_VREFDQ is only wired to TPVIA285 (a test-point), which means it is unused. SB_DIMM_VREFDQ is wired to channel 1 (not shown). Therefore, the correct `CaVrefConfig` setting for this mainboard is 2.
As to why FSP does not auto-detect this... I am not sure. While it is a mainboard-specific setting, using 2 if DDR4 is detected and 0 otherwise would work on all but the one RVP that uses config 1.