Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38523 )
Change subject: mainboard/google/hatch: Fix Puff _PR to toggle NIC ISOLATE# for S0ix ......................................................................
mainboard/google/hatch: Fix Puff _PR to toggle NIC ISOLATE# for S0ix
Turns out when going into S0ix we want the kernel to toggle de-assert to 0 for the ISOLATE# pin on the NIC for S0ix not to be woken by PCIe traffic on PCH. Upon resume the ISOLATE# pin on the NIC is then re-asserted for it to become lively again.
BUG=b:147026979 BRANCH=none TEST=Boot puff and do 1500 cycles of S0ix.
Change-Id: I3470e1edd93b461b66fc6444541a64339bcdcce3 Signed-off-by: Edward O'Callaghan quasisec@google.com --- M src/mainboard/google/hatch/variants/puff/overridetree.cb 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/38523/1
diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index e7fe907..f9ae813 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -270,6 +270,10 @@ device pci 1c.0 on chip drivers/net register "customized_leds" = "0x05af" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" + register "stop_delay_ms" = "12" # NIC needs time to quiesce + register "stop_off_delay_ms" = "1" + register "has_power_resource" = "1" device pci 00.0 on end end end # FSP requires func0 be enabled.