Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44461 )
Change subject: vc/amd/agesa/f16kb: raise the UDIMM Freq limit 1333MT/s values to 1600MT/s ......................................................................
Patch Set 4:
(4 comments)
https://review.coreboot.org/c/coreboot/+/44461/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44461/2//COMMIT_MSG@7 PS2, Line 7: MHz
MT/s (everywhere in the commit message)
Done
https://review.coreboot.org/c/coreboot/+/44461/2//COMMIT_MSG@10 PS2, Line 10: two DDR3 UDIMM modules
two DDR3 UDIMM modules *per channel*
Done
https://review.coreboot.org/c/coreboot/+/44461/2/src/vendorcode/amd/agesa/f1... File src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c:
https://review.coreboot.org/c/coreboot/+/44461/2/src/vendorcode/amd/agesa/f1... PS2, Line 96: {{_2DIMM, 2, 0, 2, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
AFAIUI (and if the comments are true, this is the frequency limit for 2 DIMMs per channel when there […]
Done
https://review.coreboot.org/c/coreboot/+/44461/2/src/vendorcode/amd/agesa/f1... PS2, Line 108: STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqKBMicroSrvUDIMM6L[] = {
I'd recommend deduplicating the arrays. For another patch, though.
Ack.