Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33225
Change subject: soc/intel/braswell/smbus.c: Add support for i2c block write ......................................................................
soc/intel/braswell/smbus.c: Add support for i2c block write
Intel Braswell supports i2c block writes using SMBus controller.
i2c_block_write() is added to configure SMBus controller in I2C mode before calling do_i2c_block_write().
Add smbus.c to ramstage.
BUG=N/A TEST=Config eDP for LCD display on Facebook FBG-1701
Change-Id: I50c1a03f624b3ab3b987d4f3b1d15dac4374e48a Signed-off-by: Frans Hendriks fhendriks@eltan.com --- M src/soc/intel/braswell/Makefile.inc M src/soc/intel/braswell/smbus.c 2 files changed, 34 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/33225/1
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index e479a3c..a7d6297 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -30,6 +30,7 @@ ramstage-y += emmc.c ramstage-y += gpio.c ramstage-y += gfx.c +ramstage-y += smbus.c
ramstage-y += gpio_support.c ramstage-y += iosf.c diff --git a/src/soc/intel/braswell/smbus.c b/src/soc/intel/braswell/smbus.c index 7e1b0df..f849926 100644 --- a/src/soc/intel/braswell/smbus.c +++ b/src/soc/intel/braswell/smbus.c @@ -3,6 +3,7 @@ * * Copyright (C) 2017 Intel Corporation. * Copyright (C) 2019 3mdeb + * Copyright (C) 2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,6 +17,11 @@
#include <device/early_smbus.h> #include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <device/pci_def.h> +#include <device/pci_type.h> +#include <device/pci_ops.h> +#include <soc/smbus.h> #include <southbridge/intel/common/smbus.h>
u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset) @@ -27,3 +33,30 @@ { return do_smbus_write_byte(SMBUS_BASE_ADDRESS, addr, offset, value); } + +int i2c_block_write(u8 smbus_devnr, u8 smbus_func, unsigned int device, u8 cmd, + u32 bytes, const u8 *buf) +{ +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC); +#else + struct device *dev = pcidev_on_root(SMBUS_DEV, SMBUS_FUNC); +#endif + u32 reg; + u32 smb_ctlr_reg; + int status; + + /* SMBus I/O BAR */ + reg = pci_read_config32(dev, PCI_BASE_ADDRESS_4) & 0xFFFFFFFE; + + /* Enable I2C_EN bit in HOSTC register */ + smb_ctlr_reg = pci_read_config32(dev, HOSTC); + pci_write_config32(dev, HOSTC, smb_ctlr_reg | HOSTC_I2C_EN); + + status = do_i2c_block_write(reg, device, cmd, bytes, buf); + + /* Restore I2C_EN bit */ + pci_write_config32(dev, HOSTC, smb_ctlr_reg); + + return status; +}