[coreboot-gerrit] Change in coreboot[master]: nb/intel/sandybridge: Do not rewrite write leveling sequence

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47616 )

Change subject: nb/intel/sandybridge: Do not rewrite write leveling sequence
......................................................................

nb/intel/sandybridge: Do not rewrite write leveling sequence

There's no need to reprogram the exact same sequence over a hundred
times. Move it out of the timB loop, and drop the `test_timB` function.

Tested on Asus P8H61-M PRO, still boots.

Change-Id: I375e325cf8b5369889b9cb059c3675cd00bdbb3f
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/sandybridge/raminit_common.c
1 file changed, 14 insertions(+), 19 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/47616/1

diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 3fdbc98..cff7e8b 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -1714,24 +1714,6 @@
    }
 }

-static void test_timB(ramctr_timing *ctrl, int channel, int slotrank)
-{
-	u32 mr1reg = make_mr1(ctrl, slotrank, channel) | 1 << 7;
-	int bank = 1;
-
-	if (ctrl->rank_mirror[channel][slotrank])
-		ddr3_mirror_mrreg(&bank, &mr1reg);
-
-	wait_for_iosav(channel);
-
-	iosav_write_jedec_write_leveling_sequence(ctrl, channel, slotrank, bank, mr1reg);
-
-	/* Execute command queue */
-	iosav_run_once(channel);
-
-	wait_for_iosav(channel);
-}
-
 static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank)
 {
    int timB;
@@ -1747,13 +1729,26 @@
    };
    MCHBAR32(GDCRTRAININGMOD) = training_mod.raw;

+	u32 mr1reg = make_mr1(ctrl, slotrank, channel) | 1 << 7;
+	int bank = 1;
+
+	if (ctrl->rank_mirror[channel][slotrank])
+		ddr3_mirror_mrreg(&bank, &mr1reg);
+
+	wait_for_iosav(channel);
+
+	iosav_write_jedec_write_leveling_sequence(ctrl, channel, slotrank, bank, mr1reg);
+
    for (timB = 0; timB < 128; timB++) {
    	FOR_ALL_LANES {
    		ctrl->timings[channel][slotrank].lanes[lane].timB = timB;
    	}
    	program_timings(ctrl, channel);

-		test_timB(ctrl, channel, slotrank);
+		/* Execute command queue */
+		iosav_run_once(channel);
+
+		wait_for_iosav(channel);

FOR_ALL_LANES {
    		statistics[lane][timB] =  !((MCHBAR32(lane_base[lane] +