Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36914 )
Change subject: binaryPI: implement C bootblock
......................................................................
Patch Set 8:
(2 comments)
https://review.coreboot.org/c/coreboot/+/36914/8/src/drivers/amd/agesa/cache...
File src/drivers/amd/agesa/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/36914/8/src/drivers/amd/agesa/cache...
PS8, Line 114: #else
Maybe just use a different file and let the Makefile do its job?
https://review.coreboot.org/c/coreboot/+/36914/8/src/drivers/amd/agesa/cache...
PS8, Line 142: OSFXSR [
Right. Would it be feasible to add it to bootblock_crt0.S? And most important, why bootblock_crt0 doesn't clear the FPU emulation bit? In fact I have copied this comment from cpu/x86/fpu_enable.inc and I wonder how true this statement is with #UD
You can just set those bits in c code before calling AGESA if you want btw.
--
To view, visit
https://review.coreboot.org/c/coreboot/+/36914
To unsubscribe, or for help writing mail filters, visit
https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I29916a96f490ff717c69dc7cd565d74a83dbfb0d
Gerrit-Change-Number: 36914
Gerrit-PatchSet: 8
Gerrit-Owner: Michał Żygowski
michal.zygowski@3mdeb.com
Gerrit-Reviewer: Kyösti Mälkki
kyosti.malkki@gmail.com
Gerrit-Reviewer: Martin Roth
martinroth@google.com
Gerrit-Reviewer: Michał Żygowski
michal.zygowski@3mdeb.com
Gerrit-Reviewer: Patrick Georgi
pgeorgi@google.com
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-CC: Arthur Heymans
arthur@aheymans.xyz
Gerrit-CC: Mike Banon
mikebdp2@gmail.com
Gerrit-CC: Paul Menzel
paulepanter@users.sourceforge.net
Gerrit-Comment-Date: Tue, 26 Nov 2019 12:50:34 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Arthur Heymans
arthur@aheymans.xyz
Comment-In-Reply-To: Michał Żygowski
michal.zygowski@3mdeb.com
Gerrit-MessageType: comment