Timothy Pearson (tpearson@raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18068
-gerrit
commit 0aecc814557d100e801502c7eed6d3c2cad49334 Author: Timothy Pearson tpearson@raptorengineering.com Date: Mon Jan 9 12:13:52 2017 -0600
amd/mct/ddr3: Fix incorrect DQ mask calculation
On AMD DDR3 platforms, the upper DQMask was incorrectly calculated, leading to undefined behaviour and possible DRAM training faults. Use the correct calculation for the upper DQMask.
Found-by: Coverity Scan #1347394 #1347393 Change-Id: If3190eb7c30f1f00d6fd8b751bc1761c9d119782 Signed-off-by: Timothy Pearson tpearson@raptorengineering.com --- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 69b0104..123b839 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -1073,7 +1073,7 @@ void read_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, Set_NB32_DCT(dev, dct, 0x27c, dword); } else if (lane < 8) { Set_NB32_DCT(dev, dct, 0x274, ~0x0); - Set_NB32_DCT(dev, dct, 0x278, ~(0xff << (lane * 8))); + Set_NB32_DCT(dev, dct, 0x278, ~(0xff << ((lane - 4) * 8))); dword = Get_NB32_DCT(dev, dct, 0x27c); dword |= 0xff; /* EccMask = 0xff */ Set_NB32_DCT(dev, dct, 0x27c, dword); @@ -1170,7 +1170,7 @@ void write_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, Set_NB32_DCT(dev, dct, 0x27c, dword); } else if (lane < 8) { Set_NB32_DCT(dev, dct, 0x274, ~0x0); - Set_NB32_DCT(dev, dct, 0x278, ~(0xff << (lane * 8))); + Set_NB32_DCT(dev, dct, 0x278, ~(0xff << ((lane - 4) * 8))); dword = Get_NB32_DCT(dev, dct, 0x27c); dword |= 0xff; /* EccMask = 0xff */ Set_NB32_DCT(dev, dct, 0x27c, dword);