Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45873 )
Change subject: lib, mb, soc: change mainboard_get_dram_part_num() prototype ......................................................................
Patch Set 3:
(8 comments)
https://review.coreboot.org/c/coreboot/+/45873/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45873/3//COMMIT_MSG@7 PS3, Line 7: lib You haven't really added this to lib in this CL. So, just "soc/intel, mb/google: "
https://review.coreboot.org/c/coreboot/+/45873/3/src/soc/intel/alderlake/rom... File src/soc/intel/alderlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/45873/3/src/soc/intel/alderlake/rom... PS3, Line 44: = 0 Not required. dram_part_num_len is always set before using.
https://review.coreboot.org/c/coreboot/+/45873/3/src/soc/intel/alderlake/rom... PS3, Line 92: part_name_overridden Why is this bool added? You can still check !dram_part_num here.
https://review.coreboot.org/c/coreboot/+/45873/3/src/soc/intel/cannonlake/ro... File src/soc/intel/cannonlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/45873/3/src/soc/intel/cannonlake/ro... PS3, Line 28: /* Default weak implementation, no need to override part number. */ return NULL;
https://review.coreboot.org/c/coreboot/+/45873/3/src/soc/intel/elkhartlake/r... File src/soc/intel/elkhartlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/45873/3/src/soc/intel/elkhartlake/r... PS3, Line 45: = 0 Same comment as alderlake.
https://review.coreboot.org/c/coreboot/+/45873/3/src/soc/intel/elkhartlake/r... PS3, Line 46: part_name_overridden Same comment as alderlake. This flag is not required.
https://review.coreboot.org/c/coreboot/+/45873/3/src/soc/intel/jasperlake/ro... File src/soc/intel/jasperlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/45873/3/src/soc/intel/jasperlake/ro... PS3, Line 45: = 0 Same comment as alderlake.
https://review.coreboot.org/c/coreboot/+/45873/3/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/45873/3/src/soc/intel/tigerlake/rom... PS3, Line 45: = 0; Not required.