[coreboot-gerrit] New patch to review for coreboot: amd/pi/stoney: Add memmap file

[Marc Jones]

Marc Jones ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18428

-gerrit

commit d568cbda5dcd1f79f44bac7a789577d054fe2806
Author: Marshall Dawson 
Date:   Sun Jan 8 14:36:46 2017 -0500

amd/pi/stoney: Add memmap file

In preparation for supporting EARLY_CBMEM_INIT, add a new file that
    will contain cbmem_top() and that can be used in all stages.  Later
    patches will also be able to use the support routines.

Original-Signed-off-by: Marshall Dawson 
    Original-Reviewed-by: Marc Jones 
    (cherry picked from commit 4fec9f6754675bbe0c8fbfc031c5c5665dace34b)

Change-Id: I8ddaa8359536081752fb8e47e49f4d5958416620
    Signed-off-by: Marc Jones 
---
 src/northbridge/amd/pi/00670F00/Makefile.inc |   3 +
 src/northbridge/amd/pi/00670F00/memmap.c     | 101 +++++++++++++++++++++++++++
 src/northbridge/amd/pi/00670F00/memmap.h     |  25 +++++++
 3 files changed, 129 insertions(+)

diff --git a/src/northbridge/amd/pi/00670F00/Makefile.inc b/src/northbridge/amd/pi/00670F00/Makefile.inc
index 7107d84..46617b9 100644
--- a/src/northbridge/amd/pi/00670F00/Makefile.inc
+++ b/src/northbridge/amd/pi/00670F00/Makefile.inc
@@ -16,3 +16,6 @@
 romstage-y += dimmSpd.c

ramstage-y += northbridge.c
+
+romstage-y += memmap.c
+ramstage-y += memmap.c
\ No newline at end of file
diff --git a/src/northbridge/amd/pi/00670F00/memmap.c b/src/northbridge/amd/pi/00670F00/memmap.c
new file mode 100644
index 0000000..02bfc13
--- /dev/null
+++ b/src/northbridge/amd/pi/00670F00/memmap.c
@@ -0,0 +1,101 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <cbmem.h>
+#include <cpu/amd/mtrr.h>
+#include "Porting.h"
+#include <AMD.h>
+#include "amdlib.h"
+#include "memmap.h"
+
+static uint32_t installed_dram(void)
+{
+	uint64_t topmem, topmem2;
+	uint32_t sysmem_mb, sysmem_gb;
+	AMD_CONFIG_PARAMS StdHeader;
+
+	LibAmdMsrRead (TOP_MEM, &topmem, &StdHeader);
+	LibAmdMsrRead (TOP_MEM2, &topmem2, &StdHeader);
+
+	if (!topmem && !topmem2)
+		return 0;
+
+	sysmem_mb = (topmem + (16ull << ONE_MB_SHIFT)) >> ONE_MB_SHIFT;
+	sysmem_mb += topmem2 ? ((topmem2 >> ONE_MB_SHIFT) - 4096) : 0;
+	sysmem_gb = sysmem_mb >> (ONE_GB_SHIFT - ONE_MB_SHIFT);
+
+	return sysmem_gb;
+}
+
+/*
+ * Return the size likely assigned to UMA when UMA_AUTO is specified.
+ * This is the only setting the wrapper currently implements.  Refer to the
+ * BKDG for Family 15h Model 70h-7Fh Procesors (PID #55072) to find the
+ * following recommended configurations:
+ *     Total system memory   UMASize
+ *        6G+                 1024M
+ *        4G                   512M
+ *        2G                   256M
+ */
+uint32_t uma_size_auto(void)
+{
+	uint32_t sysmem_gb = installed_dram();
+
+	if (sysmem_gb >= 6)
+		return 1024 << ONE_MB_SHIFT;
+	if (sysmem_gb >= 4)
+		return 512 << ONE_MB_SHIFT;
+	if (sysmem_gb >= 2)
+		return 256 << ONE_MB_SHIFT;
+	if (sysmem_gb > 0)
+		return 128 << ONE_MB_SHIFT;
+	return 0;
+}
+
+/*
+ * The BinaryPI image is compiled to always assign UMA below 4GB.  It will
+ * also adjust TOM/TOM2 for the C6 storage, as well as the audio controller.
+ */
+uint32_t uma_base_auto(void)
+{
+	uint64_t topmem;
+	AMD_CONFIG_PARAMS StdHeader;
+
+	LibAmdMsrRead (TOP_MEM, &topmem, &StdHeader);
+
+	if (!topmem)
+		return 0;
+
+	return (uint32_t)topmem - uma_size_auto();
+}
+
+#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
+unsigned long get_top_of_ram(void)
+{
+	AMD_CONFIG_PARAMS             StdHeader;
+	UINT64                        MsrReg;
+
+	LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
+	return (unsigned long)MsrReg;
+}
+#endif
+
+#if !IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
+void *cbmem_top(void)
+{
+	return (void *)uma_base_auto();
+}
+#endif
diff --git a/src/northbridge/amd/pi/00670F00/memmap.h b/src/northbridge/amd/pi/00670F00/memmap.h
new file mode 100644
index 0000000..01fcdc5
--- /dev/null
+++ b/src/northbridge/amd/pi/00670F00/memmap.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef NORTHBRIDGE_AMD_MEMMAP_H
+#define NORTHBRIDGE_AMD_MEMMAP_H
+
+#define ONE_MB_SHIFT  20
+#define ONE_GB_SHIFT  30
+
+uint32_t uma_base_auto(void);
+uint32_t uma_size_auto(void);
+
+#endif /* NORTHBRIDGE_AMD_MEMMAP_H */