[coreboot-gerrit] Change in coreboot[master]: trogdor: Add support for rev1

[Julius Werner (Code Review)]

Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38773 )

Change subject: trogdor: Add support for rev1
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trogdor: Add support for rev1

This patch implements the pin changes needed for Trogdor rev1.
Unfortunately, coreboot has to get the EC and TPM SPI busses compiled
into Kconfig, so we cannot really build a single image that runs on both
revisions. Introduce a Kconfig to handle this instead.

Change-Id: I2e48dc4565682c12089b6cf92c29f4cef4d61bb8
Signed-off-by: Julius Werner 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38773
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/trogdor/Kconfig
M src/mainboard/google/trogdor/board.h
M src/mainboard/google/trogdor/bootblock.c
3 files changed, 10 insertions(+), 5 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Julius Werner: Looks good to me, approved

diff --git a/src/mainboard/google/trogdor/Kconfig b/src/mainboard/google/trogdor/Kconfig
index 76a89fb..dfd98f0 100644
--- a/src/mainboard/google/trogdor/Kconfig
+++ b/src/mainboard/google/trogdor/Kconfig
@@ -4,6 +4,9 @@

if BOARD_GOOGLE_TROGDOR_COMMON

+config TROGDOR_REV0
+	def_bool y
+
 config BOARD_SPECIFIC_OPTIONS
    def_bool y
    select BOARD_ROMSIZE_KB_8192
@@ -32,11 +35,13 @@

config DRIVER_TPM_SPI_BUS
    hex
-	default 0x6
+	default 0x6 if TROGDOR_REV0
+	default 0x0

config EC_GOOGLE_CHROMEEC_SPI_BUS
    hex
-	default 0x0
+	default 0x0 if TROGDOR_REV0
+	default 0x6

##########################################################
 #### Update below when adding a new derivative board. ####
diff --git a/src/mainboard/google/trogdor/board.h b/src/mainboard/google/trogdor/board.h
index 93196d2..fa2fb9f 100644
--- a/src/mainboard/google/trogdor/board.h
+++ b/src/mainboard/google/trogdor/board.h
@@ -3,6 +3,7 @@
 #ifndef _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_
 #define _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_

+#include <boardid.h>
 #include <gpio.h>
 #include <soc/gpio.h>

diff --git a/src/mainboard/google/trogdor/bootblock.c b/src/mainboard/google/trogdor/bootblock.c
index b17c2e7..710a2e7 100644
--- a/src/mainboard/google/trogdor/bootblock.c
+++ b/src/mainboard/google/trogdor/bootblock.c
@@ -2,12 +2,11 @@

#include <bootblock_common.h>
 #include "board.h"
-#include <soc/qcom_qup_se.h>
 #include <soc/qupv3_spi.h>

void bootblock_mainboard_init(void)
 {
    setup_chromeos_gpios();
-	qup_spi_init(QUPV3_1_SE0, 1010 * KHz); /* H1 SPI */
-	qup_spi_init(QUPV3_0_SE0, 1010 * KHz); /* EC SPI */
+	qup_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, 1010 * KHz);
+	qup_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 1010 * KHz);
 }