[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Save DIMM info by available nodes

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39359 )

Change subject: soc/intel/tigerlake: Save DIMM info by available nodes
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Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39359/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39359/1//COMMIT_MSG@9 
PS1, Line 9: TEST= make build image returns correct dimm info by mosys and dmidecode
           :       with TGL-U and TGL-Y + MICA + LPDDR4
> that command should read mosys, not dmidecodemosys.

Based on MAX_NODE, MAX_CH and ARRAY_SIZE(mem_info->dimm), 8 entries seem correct.

For JSL, MAX_NODE is 1 and hence the old code itself looks fine. Since I don't have physical access to the mainboard, I could not verify it on the board. I can re-visit this CL if things are broken for JSL.

A question out of curiosity: for TGL 16 entries can be added(MAX_NODE: 2, MAX_CH: 4 and MAX_DIMM: 2). But only 8 entries are added because of ARRAY_SIZE(mem_info->dimm). Do we need to increase that array size in the future? Is there a reason for that limit?