Name of user not set #1002358 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33985
Change subject: include/cpu/x86: Add STM Support ......................................................................
include/cpu/x86: Add STM Support
Addtions to cpu/x86 include for STM support.
Change-Id: I2b8e68b2928aefc7996b6a9560c52f71c7c0e1d0 --- M src/include/cpu/x86/msr.h M src/include/cpu/x86/smm.h 2 files changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/33985/1
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index d1e9169..c9d92a7 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -30,6 +30,7 @@ #define IA32_BIOS_SIGN_ID 0x8b #define IA32_MPERF 0xe7 #define IA32_APERF 0xe8 +/* STM */ #define IA32_SMM_MONITOR_CTL_MSR 0x9B #define IA32_SMM_MONITOR_VALID (1<<0) #define IA32_MCG_CAP 0x179 diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index b2d7445..3bd6e41 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -512,6 +512,7 @@ struct smm_runtime { u32 smbase; u32 save_state_size; + /* useg to get the mseg address into smm for setup */ u32 mseg; /* used so that the STM can start the SMI handler in 32bit mode */ u32 start32_offset;