[coreboot-gerrit] Change in coreboot[master]: soc/intel: fix eist enabling

[Matt Delco (Code Review)]

Matt Delco has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39411 )

Change subject: soc/intel: fix eist enabling
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Patch Set 1:

This change basically takes the direction that Aaron suggested in the skylake fix.  I sympathize with the hesitation of that fix's author to add another read and write of an MSR, but 1) I don't see a way to avoid it without making larger changes to the common abstractions, and 2) I doubt anyone will notice the additional overhead.