[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp/cpx: Enable common P2SB

[Andrey Petrov (Code Review)]

Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40920 )

Change subject: soc/intel/xeon_sp/cpx: Enable common P2SB
......................................................................

soc/intel/xeon_sp/cpx: Enable common P2SB

Use common P2SB driver. This is needed to address a problem when
enumerator does not see p2sb device (since it is hidden) but it
is active and BAR is decoded.

Change-Id: I9cb821a5684f15f1e1486872bf806a6ee3d0676f
Signed-off-by: Andrey Petrov 
---
M src/soc/intel/xeon_sp/cpx/Kconfig
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/40920/1

diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
index 92681f2..15669d1 100644
--- a/src/soc/intel/xeon_sp/cpx/Kconfig
+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
@@ -74,4 +74,7 @@
      Refer to Platform FSP integration guide document to know
      the exact FSP requirement for Heap setup.

+config SOC_INTEL_COMMON_BLOCK_P2SB
+	def_bool y
+
 endif