[coreboot-gerrit] Change in coreboot[master]: sb/intel/{bd82x6x|ibexpeak}: Clear flush_* in FADT

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34453 )

Change subject: sb/intel/{bd82x6x|ibexpeak}: Clear flush_* in FADT
......................................................................

sb/intel/{bd82x6x|ibexpeak}: Clear flush_* in FADT

Both fields are ignored if WBINVD is set, which is true for all
processors since i486.

Change-Id: Ibad56046e2c1b8595dc31e5861b9fd1fd7d2d6f3
Signed-off-by: Patrick Rudolph 
---
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/ibexpeak/lpc.c
2 files changed, 6 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/34453/1

diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 8794602..e656a37 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -766,8 +766,9 @@
    }
    fadt->p_lvl2_lat = c2_latency;
    fadt->p_lvl3_lat = 87;
-	fadt->flush_size = 1024;
-	fadt->flush_stride = 16;
+	/* flush_* is ignored if ACPI_FADT_WBINVD is set */
+	fadt->flush_size = 0;
+	fadt->flush_stride = 0;
    fadt->duty_offset = 1;
    if (chip->p_cnt_throttling_supported) {
    	fadt->duty_width = 3;
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index fa1ca92..c829707 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -678,8 +678,9 @@
    }
    fadt->p_lvl2_lat = c2_latency;
    fadt->p_lvl3_lat = 87;
-	fadt->flush_size = 1024;
-	fadt->flush_stride = 16;
+	/* flush_* is ignored if ACPI_FADT_WBINVD is set */
+	fadt->flush_size = 0;
+	fadt->flush_stride = 0;
    fadt->duty_offset = 1;
    if (chip->p_cnt_throttling_supported) {
    	fadt->duty_width = 3;