[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs

[EricR Lai (Code Review)]

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Patrick Rudolph.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49136 )

Change subject: soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs
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Patch Set 6:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/49136/comment/7c3ab6bd_2702bc35 
PS6, Line 14: 
Maybe add some comment for CPU ports as well. If I was wrong you can correct it.
RP1: 0/6/0
RP2: 0/1/0 (PCIE 5.0)
RP3: 0/6/2