Liju-Clr Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72747 )
Change subject: soc/mediatek/common: Implement VM18 enable interface to supply power for BOE_TV110C9M_LL0 ......................................................................
soc/mediatek/common: Implement VM18 enable interface to supply power for BOE_TV110C9M_LL0
Implement VM18 enable interface to supply power for BOE_TV110C9M_LL0.
BUG=b:244208960 TEST=test firmware display pass for BOE_TV110C9M_LL0 on Geralt proto board
Change-Id: Ib8c3b2df1157b23b37492b1e9b1716903ea67799 Signed-off-by: Sen Chu sen.chu@mediatek.corp-partner.google.com --- M src/soc/mediatek/common/include/soc/mt6359p.h M src/soc/mediatek/common/include/soc/regulator.h M src/soc/mediatek/common/mt6359p.c 3 files changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/72747/1
diff --git a/src/soc/mediatek/common/include/soc/mt6359p.h b/src/soc/mediatek/common/include/soc/mt6359p.h index a53be63..4bb6249 100644 --- a/src/soc/mediatek/common/include/soc/mt6359p.h +++ b/src/soc/mediatek/common/include/soc/mt6359p.h @@ -33,6 +33,7 @@ PMIC_VSIM1_CON0 = 0x1cd0, PMIC_VSRAM_PROC1_ELR = 0x1b44, PMIC_VSRAM_PROC2_ELR = 0x1b46, + PMIC_VM18_CON0 = 0x1d88, PMIC_VSRAM_PROC1_VOSEL1 = 0x1e90, PMIC_VSRAM_PROC2_VOSEL1 = 0x1eb0, PMIC_VSIM1_ANA_CON0 = 0x1fa2, @@ -60,6 +61,7 @@ MT6359P_CORE, MT6359P_PA, MT6359P_SIM1, + MT6359P_VM18, MT6359P_MAX, };
@@ -84,6 +86,7 @@ u32 mt6359p_get_vsim1_voltage(void); void mt6359p_enable_vpa(bool enable); void mt6359p_enable_vsim1(bool enable); +void mt6359p_enable_vm18(bool enable); void mt6359p_write_field(u32 reg, u32 val, u32 mask, u32 shift); void pmic_init_setting(void); void pmic_lp_setting(void); diff --git a/src/soc/mediatek/common/include/soc/regulator.h b/src/soc/mediatek/common/include/soc/regulator.h index 7f3bd49..e2b9251 100644 --- a/src/soc/mediatek/common/include/soc/regulator.h +++ b/src/soc/mediatek/common/include/soc/regulator.h @@ -22,6 +22,7 @@ MTK_REGULATOR_VSRAM_PROC12, MTK_REGULATOR_VRF12, MTK_REGULATOR_VCN33, + MTK_REGULATOR_VDD18, MTK_REGULATOR_NUM, };
diff --git a/src/soc/mediatek/common/mt6359p.c b/src/soc/mediatek/common/mt6359p.c index de22b3e..fc98efc 100644 --- a/src/soc/mediatek/common/mt6359p.c +++ b/src/soc/mediatek/common/mt6359p.c @@ -324,6 +324,11 @@ mt6359p_write_field(PMIC_VSIM1_CON0, !!enable, 0x1, 0); }
+void mt6359p_enable_vm18(bool enable) +{ + mt6359p_write_field(PMIC_VM18_CON0, !!enable, 0x1, 0); +} + static void init_pmif_arb(void) { if (!pmif_arb) {