[coreboot-gerrit] Change in coreboot[master]: mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in q...

[Philipp Hug (Code Review)]

Philipp Hug has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35246 )

Change subject: mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike.
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Patch Set 3:
> Patch Set 3: Code-Review-1
>
> Tested on qemu: It hangs with MAX_CPUS=2 and -smp 1.

This is unrelated and needs to be addressed separately.
The current riscv code waits for MAX_CPUS to be ready before it proceeds to the next stage. This should be changed into a timeout.