Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50055 )
Change subject: Revert "mb/intel/shadowmountain: Add the ASL code" ......................................................................
Revert "mb/intel/shadowmountain: Add the ASL code"
This reverts commit 2151f7561d728a9280d69d20ef56a9fe44db7cb1.
Reason for revert: It depends on the shadowmountain ramstage patch.
Error on the builder:
IASL /cb-build/coreboot.0/default/INTEL_SHADOWMOUNTAIN/dsdt.aml src/mainboard/intel/shadowmountain/dsdt.asl:4:10: fatal error: baseboard/ec.h: No such file or directory #include <baseboard/ec.h> ^~~~~~~~~~~~~~~~ compilation terminated.
Change-Id: I9fa5e8cc2ad485bf82bfbda151bc46d26faef7ab Signed-off-by: Patrick Georgi pgeorgi@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/50055 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Christian Walter christian.walter@9elements.com Reviewed-by: Subrata Banik subrata.banik@intel.com Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/intel/shadowmountain/dsdt.asl 1 file changed, 0 insertions(+), 29 deletions(-)
Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Angel Pons: Looks good to me, approved Christian Walter: Looks good to me, approved
diff --git a/src/mainboard/intel/shadowmountain/dsdt.asl b/src/mainboard/intel/shadowmountain/dsdt.asl index f94ad37..c8dc9ee 100644 --- a/src/mainboard/intel/shadowmountain/dsdt.asl +++ b/src/mainboard/intel/shadowmountain/dsdt.asl @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
#include <acpi/acpi.h> -#include <baseboard/ec.h> -#include <baseboard/gpio.h>
DefinitionBlock( "dsdt.aml", @@ -14,31 +12,4 @@ ) { #include <acpi/dsdt_top.asl> - #include <soc/intel/common/block/acpi/acpi/platform.asl> - - /* global NVS and variables */ - #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> - - /* CPU */ - #include <cpu/intel/common/acpi/cpu.asl> - - Scope (_SB) { - Device (PCI0) - { - #include <soc/intel/common/block/acpi/acpi/northbridge.asl> - #include <soc/intel/alderlake/acpi/southbridge.asl> - #include <soc/intel/alderlake/acpi/tcss.asl> - } - } - - /* Chrome OS Embedded Controller */ - Scope (_SB.PCI0.LPCB) - { - // ACPI code for EC SuperIO functions - #include <ec/google/chromeec/acpi/superio.asl> - // ACPI code for EC functions - #include <ec/google/chromeec/acpi/ec.asl> - } - - #include <southbridge/intel/common/acpi/sleepstates.asl> }