Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47599 )
Change subject: arch/x86: Top align bootblock program ......................................................................
arch/x86: Top align bootblock program
Change-Id: If32518b1c19d08935727330314904b52a246af3c Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/arch/x86/bootblock_crt0.S M src/arch/x86/memlayout.ld M src/arch/x86/walkcbfs.S M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/p3/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/microcode/microcode_asm.S M src/cpu/x86/16bit/entry16.inc M src/cpu/x86/16bit/reset16.ld M src/drivers/amd/agesa/cache_as_ram.S M src/soc/amd/common/block/cpu/car/cache_as_ram.S 12 files changed, 62 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/47599/1
diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 3f41464..20262eb 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -10,7 +10,7 @@
#include <cpu/x86/cr.h>
-.section .text +.section ".init", "ax", @progbits
/* * Include the old code for reset vector and protected mode entry. That code has @@ -53,3 +53,5 @@
/* We're done. Now it's up to platform-specific code */ jmp bootblock_pre_c_entry + +.previous diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index b487e48..a68dac5 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -28,8 +28,6 @@
#include "car.ld" #elif ENV_BOOTBLOCK - BOOTBLOCK(0xffffffff - CONFIG_C_ENV_BOOTBLOCK_SIZE + 1, - CONFIG_C_ENV_BOOTBLOCK_SIZE)
#include "car.ld"
diff --git a/src/arch/x86/walkcbfs.S b/src/arch/x86/walkcbfs.S index b8d4fb9..66b97e3b 100644 --- a/src/arch/x86/walkcbfs.S +++ b/src/arch/x86/walkcbfs.S @@ -21,7 +21,7 @@ #define CBFS_FILE_STRUCTSIZE (CBFS_FILE_OFFSET + 4)
.code32 -.section .text +.section ".init" .global walkcbfs_asm
/* @@ -121,3 +121,5 @@
filemagic: .ascii "LARCHIVE" + +.previous diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 837394c..40cd60d 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -4,6 +4,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h>
+.section ".init" .global bootblock_pre_c_entry
.code32 @@ -190,3 +191,4 @@ fixed_mtrr_list_size = . - fixed_mtrr_list
_cache_as_ram_setup_end: +.previous diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index cde1ca3..1846408 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -7,6 +7,7 @@ #define NoEvictMod_MSR 0x2e0 #define BBL_CR_CTL3_MSR 0x11e
+.section ".init" .global bootblock_pre_c_entry
#include <cpu/intel/car/cache_as_ram_symbols.inc> @@ -257,3 +258,4 @@ fixed_mtrr_list_size = . - fixed_mtrr_list
_cache_as_ram_setup_end: +.previous diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index 71e3447..b48afac 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -4,6 +4,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h>
+.section ".init" .global bootblock_pre_c_entry
.code32 @@ -179,3 +180,4 @@ fixed_mtrr_list_size = . - fixed_mtrr_list
_cache_as_ram_setup_end: +.previous diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 4e36538..b02fced 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -8,6 +8,7 @@ /* Macro to access Local APIC registers at default base. */ #define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x)
+.section ".init" .global bootblock_pre_c_entry
.code32 @@ -390,3 +391,4 @@ fixed_mtrr_list_size = . - fixed_mtrr_list
_cache_as_ram_setup_end: +.previous diff --git a/src/cpu/intel/microcode/microcode_asm.S b/src/cpu/intel/microcode/microcode_asm.S index f02351a..8bef63d 100644 --- a/src/cpu/intel/microcode/microcode_asm.S +++ b/src/cpu/intel/microcode/microcode_asm.S @@ -43,7 +43,7 @@ * if the revision of the update is newer than what is installed */
-.section .text +.section ".init" .global update_bsp_microcode
update_bsp_microcode: @@ -151,3 +151,5 @@ .string "cpu_microcode_blob.bin"
_update_bsp_microcode_end: + +.previous diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 13d12be..e9ebac6 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -28,10 +28,9 @@ #include <arch/rom_segs.h> #include <cpu/x86/post_code.h>
-/* Symbol _start16bit must be aligned to 4kB to start AP CPUs with - * Startup IPI message without RAM. +/* Symbol _start16bit must reachable from the reset vector, and be aligned to + * 4kB to start AP CPUs with Startup IPI message without RAM. */ -.align 4096 .code16 .globl _start16bit .type _start16bit, @function diff --git a/src/cpu/x86/16bit/reset16.ld b/src/cpu/x86/16bit/reset16.ld index d356034..be1209a 100644 --- a/src/cpu/x86/16bit/reset16.ld +++ b/src/cpu/x86/16bit/reset16.ld @@ -11,14 +11,28 @@ ap_sipi_vector_in_rom = (_start16bit >> 12) & 0xff; #endif
-/* - * _ROMTOP : The top of the ROM used where we - * need to put the reset vector. - */ - SECTIONS { - /* Trigger an error if I have an unuseable start address */ - _bogus = ASSERT(_start16bit >= 0xffff0000, "_start16bit too low. Please report."); + . = BOOTBLOCK_TOP - PROGRAM_SZ; + . = ALIGN(16); + + _bootblock = .; + + INCLUDE "bootblock/lib/program.ld" + + . = ID_SECTION - EARLYASM_SZ; + . = CONFIG(SIPI_VECTOR_IN_ROM) ? ALIGN(4096) : ALIGN(16); + BOOTBLOCK_TOP = .; + .init . : { + *(.init); + } + + /* + * Allocation reserves extra space here. Alignment requirements + * may cause the total size of a section to change when the start + * address gets applied. + */ + PROGRAM_SZ = SIZEOF(.text) + 32; + EARLYASM_SZ = SIZEOF(.init) + (CONFIG(SIPI_VECTOR_IN_ROM) ? 4096 : 16);
. = ID_SECTION; .id (.): { @@ -40,4 +54,9 @@ . = 15; BYTE(0x00); } + _ebootblock = .; } + +_bogus1 = ASSERT(_bootblock & 0x80000000, "Invalid linker script"); +_bogus2 = ASSERT(_start16bit & 0x80000000, "Invalid linker script"); +_bogus3 = ASSERT(_start16bit >= 0xffff0000, "_start16bit too low. Please report."); diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 8e7ea29..9235008 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -10,16 +10,19 @@ ****************************************************************************** */
-#include "gcccar.inc" #include <cpu/x86/lapic_def.h> #include <cpu/x86/post_code.h>
+.section ".init" + .code32 .globl _cache_as_ram_setup, _cache_as_ram_setup_end .global bootblock_pre_c_entry
_cache_as_ram_setup:
+#include "gcccar.inc" + /* * on entry: * mm0: BIST (ignored) @@ -73,3 +76,4 @@ jmp stop
_cache_as_ram_setup_end: +.previous diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S index 3eb7670..9d35d5c 100644 --- a/src/soc/amd/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S @@ -8,9 +8,17 @@ ****************************************************************************** */
-#include "gcccar.inc" #include <cpu/x86/post_code.h>
+.section ".init" + +.code32 +.globl _cache_as_ram_setup, _cache_as_ram_setup_end + +_cache_as_ram_setup: + +#include "gcccar.inc" + /* * on entry: * mm0: BIST (ignored) @@ -43,3 +51,6 @@ post_code(POST_DEAD_CODE) hlt jmp .halt_forever + +_cache_as_ram_setup_end: +.previous