build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41062 )
Change subject: soc/intel/jasperlake: Apply FiVR related settings ......................................................................
Patch Set 10:
(3 comments)
https://review.coreboot.org/c/coreboot/+/41062/10/src/soc/intel/jasperlake/f... File src/soc/intel/jasperlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/41062/10/src/soc/intel/jasperlake/f... PS10, Line 182: /* Retention Mode Voltage to Low Current Mode Voltage transition time in 1us resolution - 44 us */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/41062/10/src/soc/intel/jasperlake/f... PS10, Line 184: /* Retention Mode Voltage to High Current Mode Voltage transition time in 1us resolution - 54 us */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/41062/10/src/soc/intel/jasperlake/f... PS10, Line 186: /* Low Current Mode Voltage to High Current Mode Voltage transition time in 1us resolution - 13 us */ line over 96 characters