HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42189 )
Change subject: nb/intel/gm45: Use PCI bitwise ops ......................................................................
Patch Set 3: Code-Review+1
(3 comments)
https://review.coreboot.org/c/coreboot/+/42189/3/src/northbridge/intel/gm45/... File src/northbridge/intel/gm45/early_reset.c:
https://review.coreboot.org/c/coreboot/+/42189/3/src/northbridge/intel/gm45/... PS3, Line 43: MCHBAR32(DCC_MCHBAR) = : (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_CMD_NOP; not related
https://review.coreboot.org/c/coreboot/+/42189/3/src/northbridge/intel/gm45/... File src/northbridge/intel/gm45/gma.c:
https://review.coreboot.org/c/coreboot/+/42189/3/src/northbridge/intel/gm45/... PS3, Line 34: const u16 cdclk_sel = : pci_read_config16 (dev, GCFGC_OFFSET) & GCFGC_CD_MASK; not related
https://review.coreboot.org/c/coreboot/+/42189/3/src/northbridge/intel/gm45/... File src/northbridge/intel/gm45/pcie.c:
https://review.coreboot.org/c/coreboot/+/42189/3/src/northbridge/intel/gm45/... PS3, Line 217: 0x01 << 29 just '1 << 29'?