Attention is currently required from: Jakub Czapiga, Sukumar Ghorai.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78177?usp=email )
The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: soc/intel: Fix cpu-pc10 residency counter frequency in LPIT table ......................................................................
Patch Set 4:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/78177/comment/d47cb9ac_c739db2e : PS4, Line 9: Table(LPIT) Please add a space before the (.
https://review.coreboot.org/c/coreboot/+/78177/comment/614061ff_02249cad : PS4, Line 12: read via memory mapped … IO?
https://review.coreboot.org/c/coreboot/+/78177/comment/19c1335b_6501ebc3 : PS4, Line 14: https://www.uefi.org/sites/default/files/resources/ : Intel_ACPI_Low_Power_S0_Idle.pdf The URL should be one line.
https://review.coreboot.org/c/coreboot/+/78177/comment/5f6a68b0_490563fd : PS4, Line 23: cat /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us What device? What do you check exactly? Before your patch it was 0?
File src/soc/intel/common/block/acpi/lpit.c:
https://review.coreboot.org/c/coreboot/+/78177/comment/c3781ec7_363fe4d2 : PS4, Line 34: pkg_counter->counter_frequency = 0; /* same freq as TSC */ The macro is defined as 0.
src/include/acpi/acpi.h:#define ACPI_LPIT_CTR_FREQ_TSC 0
What is the difference?