Hello Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37491
to look at the new patch set (#3).
Change subject: x86: Implement a romstage-only version of RESET_VECTOR_IN_RAM ......................................................................
x86: Implement a romstage-only version of RESET_VECTOR_IN_RAM
In continuing the flexibility of RESET_VECTOR_IN_RAM, add Kconfig options for declaring whether the first stage of execution is bootblock or romstage. For the romstage version, rely on the existing x86 reset vector handling and initialization, as well as assembly_entry.S (previously intended only to reinitialize the x86's basic settings in early stages).
Add a new function to be called earlyram_stage_entry() that transmits the BIST information to be checked.
Adjust linker scripts accordingly.
Note that flipping the default build to a hybrid romstage arrangement is intentional. Implementations intending to use a traditional bootblock should select RESET_VECTOR_IN_RAM_BOOTBLOCK.
Sample build using amd/mandolin (currently WIP): Name Offset Type Size Comp cbfs master header 0x0 cbfs header 32 none fallback/ramstage 0x80 stage 76253 none config 0x12ac0 raw 300 none revision 0x12c40 raw 674 none payload_config 0x12f40 raw 1621 none payload_revision 0x13600 raw 264 none (empty) 0x13780 null 1560 none fspm.bin 0x13dc0 fsp 720896 none (empty) 0xc3e00 null 3992 none fsps.bin 0xc4dc0 fsp 327680 none pci1002,15d8.rom 0x114e00 optionrom 54272 none fallback/dsdt.aml 0x122280 raw 8372 none fallback/payload 0x124380 simple elf 69495 none (empty) 0x135340 null 2927128 none bootblock 0x3ffd80 bootblock 64 none
readelf of build/cbfs/fallback/romstage.elf: Section Headers: [Nr] Name Type Addr Off Size ES Flg Lk Inf Al [ 0] NULL 00000000 000000 000000 00 0 0 0 [ 1] .text PROGBITS 08000000 001000 007ba0 00 AX 0 0 32 [ 2] .rel.text REL 00000000 083938 001ab0 08 I 9 1 4 [ 3] .earlyram.data NOBITS 0802cf4a 008ba0 045f8e 00 WA 0 0 32 [ 4] .near_reset_vecto PROGBITS 0807f000 080000 0000c8 00 AX 0 0 4096 [ 5] .rel.near_reset_v REL 00000000 0853e8 000058 08 I 9 4 4 [ 6] .reset PROGBITS 0807fff0 080ff0 000010 00 AX 0 0 1 [ 7] .rel.reset REL 00000000 085440 000008 08 I 9 6 4 [ 8] .gnu_debuglink PROGBITS 00000000 081000 000014 00 0 0 4 [ 9] .symtab SYMTAB 00000000 081014 0015b0 10 10 123 4 [10] .strtab STRTAB 00000000 0825c4 001373 00 0 0 1 [11] .shstrtab STRTAB 00000000 085448 000065 00 0 0 1
169: 0802cf50 0 NOTYPE GLOBAL DEFAULT 3 _earlyram_stack 135: 0802d750 0 NOTYPE GLOBAL DEFAULT 3 _eearlyram_stack 276: 0802d750 0 NOTYPE GLOBAL DEFAULT 3 _preram_cbmem_console 312: 0802ed50 0 NOTYPE GLOBAL DEFAULT 3 _epreram_cbmem_console 204: 0802ed50 0 NOTYPE GLOBAL DEFAULT 3 _timestamp 337: 0802ef50 0 NOTYPE GLOBAL DEFAULT 3 _etimestamp 159: 0802ef50 0 NOTYPE GLOBAL DEFAULT 3 _fmap_cache 201: 0802f006 0 NOTYPE GLOBAL DEFAULT 3 _efmap_cache 246: 0802f008 0 NOTYPE GLOBAL DEFAULT 3 _bss 218: 08072ed8 0 NOTYPE GLOBAL DEFAULT 3 _ebss
Change-Id: Ida2bc90fdd3e953445065929124adaa168164250 Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com --- M Makefile.inc M src/arch/x86/Kconfig M src/arch/x86/Makefile.inc M src/arch/x86/assembly_entry.S M src/arch/x86/include/arch/cpu.h M src/arch/x86/memlayout.ld M src/cpu/x86/32bit/entry32.inc 7 files changed, 50 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/37491/3