Attention is currently required from: Angel Pons, Piotr Król.
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67940 )
Change subject: mb/protectli/vault_cml: Add Comet Lake 6 port board support ......................................................................
Patch Set 16:
(7 comments)
File src/mainboard/protectli/vault_cml/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/67940/comment/40603c72_c3646191 PS7, Line 287: device pci 1f.1 on end # P2SB : device pci 1f.2 on end # Power Management Controller
Marked them both as hidden. Is that fine for you? […]
It still works. I don't think having these devices set to 'ON' had anything to do with those issues, as these devices were simply not visible at all. In fact, I recall not including the VBT actually helped, so I could have a buggy VBT earlier.
File src/mainboard/protectli/vault_cml/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/67940/comment/4a1403bd_a260f258 PS13, Line 55: register "SataMode" = "0"
This should be dropped too. SATA mode should be a Kconfig option instead, anyway.
Done
https://review.coreboot.org/c/coreboot/+/67940/comment/1845cf7a_167a5640 PS13, Line 67: register "PcieRpEnable[13]" = "1" : register "PcieRpEnable[14]" = "1" : register "PcieRpEnable[15]" = "1"
As root port 13 (array index 12) is x4, these three root ports do not have any lanes associated to t […]
Done
https://review.coreboot.org/c/coreboot/+/67940/comment/d9818a92_e787a0fa PS13, Line 80: register "PcieRpAdvancedErrorReporting[13]" = "1" : register "PcieRpAdvancedErrorReporting[14]" = "1" : register "PcieRpAdvancedErrorReporting[15]" = "1"
Same as above
Done
https://review.coreboot.org/c/coreboot/+/67940/comment/c2cdb44d_ed9981b2 PS13, Line 93: register "PcieRpLtrEnable[13]" = "1" : register "PcieRpLtrEnable[14]" = "1" : register "PcieRpLtrEnable[15]" = "1"
Same as above
Done
https://review.coreboot.org/c/coreboot/+/67940/comment/27f7703c_7b799d07 PS13, Line 202: device pci 1d.5 on end # PCI Express Port 14 : device pci 1d.6 on end # PCI Express Port 15 : device pci 1d.7 on end # PCI Express Port 16
Same as the FSP settings. These root ports have no lanes associated to them (`device pci 1d. […]
Done
File src/mainboard/protectli/vault_cml/die.c:
https://review.coreboot.org/c/coreboot/+/67940/comment/65ace1e2_7d0e6a08 PS13, Line 12: static uint8_t beep_count = 0;;
Statements terminations use 1 semicolon […]
Done