Attention is currently required from: Hung-Te Lin, Yu-Ping Wu.
Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63252 )
Change subject: soc/mediatek: Fill coreboot table with PCIe info
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63252/comment/cb1b88be_827ab1bc
PS3, Line 9: F
In order to pass PCIe base address to payloads, implement pcie_fill_lb() to fill coreboot ...
Done
--
To view, visit
https://review.coreboot.org/c/coreboot/+/63252
To unsubscribe, or for help writing mail filters, visit
https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib2988694f60aac9cbfc09ef9a26d47e01c004406
Gerrit-Change-Number: 63252
Gerrit-PatchSet: 4
Gerrit-Owner: Jianjun Wang
jianjun.wang@mediatek.com
Gerrit-Reviewer: Hung-Te Lin
hungte@chromium.org
Gerrit-Reviewer: Yu-Ping Wu
yupingso@google.com
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-Attention: Hung-Te Lin
hungte@chromium.org
Gerrit-Attention: Yu-Ping Wu
yupingso@google.com
Gerrit-Comment-Date: Fri, 01 Apr 2022 06:30:37 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Yu-Ping Wu
yupingso@google.com
Gerrit-MessageType: comment