Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74801 )
Change subject: mb/siemens/mc_ehl: Remove wrong comment regarding spd.bin ......................................................................
mb/siemens/mc_ehl: Remove wrong comment regarding spd.bin
The support for a spd.bin from CBFS was removed for all mc_ehl boards in commit 833bb448c5213 (mb/siemens/mc_ehl: Remove spd.bin from CBFS). There is still a remaining comment in romstage_fsp_params.c referring to the removed capability. This fix removes the spd.bin related part of the comment to stay consistent with the code.
Change-Id: I669ee1c33d1d1c47764640982f71129195e63f14 Signed-off-by: Werner Zeh werner.zeh@siemens.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/74801 Reviewed-by: Jan Samek jan.samek@siemens.com Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Mario Scheithauer mario.scheithauer@siemens.com Reviewed-by: Paul Menzel paulepanter@mailbox.org --- M src/mainboard/siemens/mc_ehl/romstage_fsp_params.c 1 file changed, 22 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Mario Scheithauer: Looks good to me, approved Jan Samek: Looks good to me, but someone else must approve
diff --git a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c index 506bcc6..98c9348 100644 --- a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c +++ b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c @@ -17,8 +17,7 @@ static uint8_t spd_data[CONFIG_DIMM_SPD_SIZE]; const char *cbfs_hwi_name = "hwinfo.hex";
- /* Initialize SPD information for LPDDR4x from HW-Info primarily with a fallback to - spd.bin in the case where the SPD data in HW-Info is not available or invalid. */ + /* Initialize SPD information for LPDDR4x from HW-Info. */ memset(spd_data, 0, sizeof(spd_data)); if ((hwilib_find_blocks(cbfs_hwi_name) == CB_SUCCESS) && (hwilib_get_field(SPD, spd_data, 0x80) == 0x80) &&