[coreboot-gerrit] [L] Change in coreboot[main]: Introduce a coreboot Control Block (CCB)

[Simon Glass (Code Review)]

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Jérémy Compostella, Karthik Ramasubramanian, Paul Menzel.

Simon Glass has posted comments on this change by Simon Glass. ( https://review.coreboot.org/c/coreboot/+/77712?usp=email )

Change subject: Introduce a coreboot Control Block (CCB)
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Patch Set 10:

(3 comments)

Patchset:

PS10:
> > So long as you can access the flash early in the bootblock, then that can work. […]

My objection is the -2. I am happy to address comments but there is no point if the whole thing is blocked.

The tricky thing here is reading the CCB early enough that it can affect the first console output. Putting the CCB in the bootblock is simpler on some boards since it doesn't require reading the SPI flash very early in bootblock (before console).

File src/arch/x86/postcar.c:

https://review.coreboot.org/c/coreboot/+/77712/comment/22bcf9dc_d2a401a8?usp... :
PS10, Line 21: console_init();
> This is done with a reason: so you can debug cbmem init.

Right...so how should we proceed? cbmem_initialize() does produce console output. CCB won't affect that unless you manually ask it to be silent by updating the CCB in the ROM

File util/cbfstool/cbfstool.c:

https://review.coreboot.org/c/coreboot/+/77712/comment/7852857c_b5a6d4fe?usp... :
PS10, Line 112: 	const char *value;
> is this used?

Yes, see:

param.value = optarg