Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36032 )
Change subject: soc/intel/{cnl, icl}: Update the DCACHE_BSP_STACK_SIZE to 129KiB ......................................................................
Patch Set 4: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/36032/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36032/4//COMMIT_MSG@9 PS4, Line 9: The current DCACHE_BSP_STACK_SIZE is set to 128KiB for CML & ICL when FSP uses : the same stack provided by coreboot. This patch updates it to 129KiB since the default : value of DCACHE_BSP_STACK_SIZE must be the sum of FSP-M stack requirement (128KiB) : and CB romstage stack requirement (~1KiB). This is exceeding the 75 char linelength however.
https://review.coreboot.org/c/coreboot/+/36032/4/src/soc/intel/cannonlake/Kc... File src/soc/intel/cannonlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/36032/4/src/soc/intel/cannonlake/Kc... PS4, Line 128: sum of FSP-M stack requirement (128KiB) and CB romstage stack requirement (~1KiB).
This is within the current limit on the length of lines which is 96 columns. […]
For Kconfig option it's nice to have them fit in 80x25 terminals, but searching for this symbol does not show this one.