Duncan Laurie (dlaurie@chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18084
-gerrit
commit 9190f4d316edb467e6ee34ce56cb47d444124e89 Author: Duncan Laurie dlaurie@chromium.org Date: Mon Jan 9 22:23:39 2017 -0800
skylake: Do not pass VBT to FSP if display init not required
The FSP 2.0 change broke the logic for determining whether or not to execute the GOP binary. Modify the FSP 2.0 code to do the right thing and check for display_init_required() before passing VBT into FSP and the GOP binary.
BUG=chrome-os-partner:61726 TEST=disable developer mode and ensure FSP does not run GOP
Change-Id: I7fc8055b6664e0cf231a8de34367406eb049dfe1 Signed-off-by: Duncan Laurie dlaurie@chromium.org --- src/soc/intel/skylake/chip_fsp20.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index a1e76a9..2aef65a 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -14,6 +14,7 @@ */
#include <chip.h> +#include <bootmode.h> #include <bootstate.h> #include <device/pci.h> #include <fsp/api.h> @@ -108,9 +109,18 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) mainboard_silicon_init_params(params);
/* Load VBT */ - if (!is_s3_wakeup) + if (is_s3_wakeup) { + printk(BIOS_DEBUG, "S3 resume do not pass VBT to GOP\n"); + } else if (display_init_required()) { + /* Get VBT data */ vbt_data = fsp_load_vbt(); - + if (vbt_data) + printk(BIOS_DEBUG, "Passing VBT to GOP\n"); + else + printk(BIOS_DEBUG, "VBT not found!\n"); + } else { + printk(BIOS_DEBUG, "Not passing VBT to GOP\n"); + } params->GraphicsConfigPtr = (u32) vbt_data;
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {