Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Jason Nien, Martin Roth, Matt DeVillier.
Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86273?usp=email )
Change subject: soc/amd/mendocino/chipset_*: Enable gpp_bridge_[a/b/c] by default ......................................................................
soc/amd/mendocino/chipset_*: Enable gpp_bridge_[a/b/c] by default
TODO justification
Change-Id: Ife30f73495d44c98717e147602de10f5a6a89358 Signed-off-by: Maximilian Brune maximilian.brune@9elements.com --- M src/mainboard/google/skyrim/variants/baseboard/devicetree.cb M src/soc/amd/mendocino/chipset_mendocino.cb M src/soc/amd/mendocino/chipset_rembrandt.cb 3 files changed, 6 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/86273/1
diff --git a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb index fe6537f..302d289 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb @@ -173,6 +173,7 @@ device ref acp on end # Audio Processor (ACP) device ref mp2 on end # Sensor Fusion Hub (MP2) end + device ref gpp_bridge_b on # Internal GPP Bridge 1 to Bus B device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C device ref xhci_2 on # USB 2.0 (USB2) ops xhci_pci_ops diff --git a/src/soc/amd/mendocino/chipset_mendocino.cb b/src/soc/amd/mendocino/chipset_mendocino.cb index 6ee1e63..3458cae 100644 --- a/src/soc/amd/mendocino/chipset_mendocino.cb +++ b/src/soc/amd/mendocino/chipset_mendocino.cb @@ -16,7 +16,7 @@ device pci 02.4 alias gpp_bridge_3 hidden ops amd_external_pcie_gpp_ops end
device pci 08.0 on end # Dummy device function, do not disable - device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A + device pci 08.1 alias gpp_bridge_a on # Internal GPP Bridge 0 to Bus A ops amd_internal_pcie_gpp_ops device pci 0.0 alias gfx off ops amd_graphics_ops end # Internal GPU (GFX) device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ) @@ -65,7 +65,7 @@ device pci 0.6 alias hda off end # Audio Processor HD Audio Controller (main AZ) device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2) end - device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C + device pci 08.3 alias gpp_bridge_c on # Internal GPP Bridge 2 to Bus C ops amd_internal_pcie_gpp_ops device pci 0.0 alias xhci_2 off end # Might also be a dummy device with different PCI DID # When using this as XHCI2, the mainboard devicetree needs to add ops xhci_pci_ops diff --git a/src/soc/amd/mendocino/chipset_rembrandt.cb b/src/soc/amd/mendocino/chipset_rembrandt.cb index ef3bfa9..aef0a89 100644 --- a/src/soc/amd/mendocino/chipset_rembrandt.cb +++ b/src/soc/amd/mendocino/chipset_rembrandt.cb @@ -18,7 +18,7 @@ device pci 02.6 alias gpp_bridge_5 hidden ops amd_external_pcie_gpp_ops end
device pci 08.0 on end # Dummy device function, do not disable - device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A + device pci 08.1 alias gpp_bridge_a on # Internal GPP Bridge 0 to Bus A ops amd_internal_pcie_gpp_ops device pci 0.0 alias gfx off ops amd_graphics_ops end # Internal GPU (GFX) device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ) @@ -67,8 +67,8 @@ device pci 0.6 alias hda off end # Audio Processor HD Audio Controller (main AZ) device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2) end - device pci 08.2 alias gpp_bridge_b off ops amd_internal_pcie_gpp_ops end # Internal GPP Bridge 1 to Bus B - device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C + device pci 08.2 alias gpp_bridge_b on ops amd_internal_pcie_gpp_ops end # Internal GPP Bridge 1 to Bus B + device pci 08.3 alias gpp_bridge_c on # Internal GPP Bridge 2 to Bus C ops amd_internal_pcie_gpp_ops device pci 0.0 alias xhci_2 off end # Might also be a dummy device with different PCI DID # When using this as XHCI2, the mainboard devicetree needs to add ops xhci_pci_ops