Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11413
-gerrit
commit 48827a7b6103450dc4d3e974cf95185ff85a04eb Author: Duncan Laurie dlaurie@chromium.org Date: Mon Aug 17 18:09:14 2015 -0700
fsp raminit: Add romstage_params to soc_memory_init_params
The SOC handler for memory init params is only taking UPD as an input which does not allow it to use romstage_params. In addition the UPD input is called params which is confusing so rename it to upd so romstage_params can be passed properly.
BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados p2
Change-Id: I414610fee2b5d03a8e2cebfa548ea8bf49932a48 Signed-off-by: Patrick Georgi patrick@georgi-clan.de Original-Commit-Id: db94d6f3e6cad721de2188a136df10ccf66aff6a Original-Change-Id: I7ec15edd4a16df121c5967aadd8b2651267ec773 Original-Signed-off-by: Duncan Laurie dlaurie@chromium.org Original-Reviewed-on: https://chromium-review.googlesource.com/294066 Original-Reviewed-by: Aaron Durbin adurbin@chromium.org --- src/soc/intel/braswell/romstage/romstage.c | 21 ++++++++--------- src/soc/intel/common/raminit.c | 6 +++-- src/soc/intel/common/romstage.h | 3 ++- src/soc/intel/skylake/romstage/romstage.c | 36 +++++++++++++++--------------- 4 files changed, 35 insertions(+), 31 deletions(-)
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 64a3dee..1dbff54 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -203,7 +203,8 @@ void soc_after_ram_init(struct romstage_params *params) }
/* Initialize the UPD parameters for MemoryInit */ -void soc_memory_init_params(MEMORY_INIT_UPD *params) +void soc_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *upd) { const struct device *dev; const struct soc_intel_braswell_config *config; @@ -212,16 +213,16 @@ void soc_memory_init_params(MEMORY_INIT_UPD *params) dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); config = dev->chip_info; printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n"); - params->PcdMrcInitTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? + upd->PcdMrcInitTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? config->PcdMrcInitTsegSize : 0; - params->PcdMrcInitMmioSize = config->PcdMrcInitMmioSize; - params->PcdMrcInitSpdAddr1 = config->PcdMrcInitSpdAddr1; - params->PcdMrcInitSpdAddr2 = config->PcdMrcInitSpdAddr2; - params->PcdIgdDvmt50PreAlloc = config->PcdIgdDvmt50PreAlloc; - params->PcdApertureSize = config->PcdApertureSize; - params->PcdGttSize = config->PcdGttSize; - params->PcdLegacySegDecode = config->PcdLegacySegDecode; - params->PcdDvfsEnable = config->PcdDvfsEnable; + upd->PcdMrcInitMmioSize = config->PcdMrcInitMmioSize; + upd->PcdMrcInitSpdAddr1 = config->PcdMrcInitSpdAddr1; + upd->PcdMrcInitSpdAddr2 = config->PcdMrcInitSpdAddr2; + upd->PcdIgdDvmt50PreAlloc = config->PcdIgdDvmt50PreAlloc; + upd->PcdApertureSize = config->PcdApertureSize; + upd->PcdGttSize = config->PcdGttSize; + upd->PcdLegacySegDecode = config->PcdLegacySegDecode; + upd->PcdDvfsEnable = config->PcdDvfsEnable; }
void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, diff --git a/src/soc/intel/common/raminit.c b/src/soc/intel/common/raminit.c index 69ae114..ddf5675 100644 --- a/src/soc/intel/common/raminit.c +++ b/src/soc/intel/common/raminit.c @@ -100,7 +100,7 @@ void raminit(struct romstage_params *params) fsp_memory_init_params.HobListPtr = &hob_list_ptr;
/* Update the UPD data */ - soc_memory_init_params(&memory_init_params); + soc_memory_init_params(params, &memory_init_params); mainboard_memory_init_params(params, &memory_init_params); post_code(0x36);
@@ -309,7 +309,9 @@ __attribute__((weak)) void soc_display_memory_init_params( }
/* Initialize the UPD parameters for MemoryInit */ -__attribute__((weak)) void soc_memory_init_params(MEMORY_INIT_UPD *params) +__attribute__((weak)) void soc_memory_init_params( + struct romstage_params *params, + MEMORY_INIT_UPD *upd) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } diff --git a/src/soc/intel/common/romstage.h b/src/soc/intel/common/romstage.h index 403016e..440cad7 100644 --- a/src/soc/intel/common/romstage.h +++ b/src/soc/intel/common/romstage.h @@ -93,7 +93,8 @@ void soc_after_ram_init(struct romstage_params *params); void soc_after_temp_ram_exit(void); void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, MEMORY_INIT_UPD *new); -void soc_memory_init_params(MEMORY_INIT_UPD *params); +void soc_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *upd); void soc_pre_console_init(struct romstage_params *params); void soc_pre_ram_init(struct romstage_params *params); void soc_romstage_init(struct romstage_params *params); diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 2ce5ce3..91a496e 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -77,33 +77,33 @@ int vboot_get_sw_write_protect(void) #endif
/* UPD parameters to be initialized before MemoryInit */ -void soc_memory_init_params(MEMORY_INIT_UPD *params) +void soc_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *upd) { const struct device *dev; const struct soc_intel_skylake_config *config;
- /* Set the parameters for MemoryInit */ dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); config = dev->chip_info;
- memcpy(params->PcieRpEnable, config->PcieRpEnable, - sizeof(params->PcieRpEnable)); - memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport, - sizeof(params->PcieRpClkReqSupport)); - memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, - sizeof(params->PcieRpClkReqNumber)); + memcpy(upd->PcieRpEnable, config->PcieRpEnable, + sizeof(upd->PcieRpEnable)); + memcpy(upd->PcieRpClkReqSupport, config->PcieRpClkReqSupport, + sizeof(upd->PcieRpClkReqSupport)); + memcpy(upd->PcieRpClkReqNumber, config->PcieRpClkReqNumber, + sizeof(upd->PcieRpClkReqNumber));
- params->MmioSize = 0x800; /* 2GB in MB */ - params->TsegSize = CONFIG_SMM_TSEG_SIZE; - params->IedSize = CONFIG_IED_REGION_SIZE; - params->ProbelessTrace = config->ProbelessTrace; - params->EnableLan = config->EnableLan; - params->EnableSata = config->EnableSata; - params->SataMode = config->SataMode; - params->EnableTraceHub = config->EnableTraceHub; - params->SaGv = config->SaGv; - params->RMT = config->Rmt; + upd->MmioSize = 0x800; /* 2GB in MB */ + upd->TsegSize = CONFIG_SMM_TSEG_SIZE; + upd->IedSize = CONFIG_IED_REGION_SIZE; + upd->ProbelessTrace = config->ProbelessTrace; + upd->EnableLan = config->EnableLan; + upd->EnableSata = config->EnableSata; + upd->SataMode = config->SataMode; + upd->EnableTraceHub = config->EnableTraceHub; + upd->SaGv = config->SaGv; + upd->RMT = config->Rmt; }
void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,