Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38768 )
Change subject: [UNTESTED] intel/stm: Introduce stm_update_smm_info() ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38768/2/src/security/intel/stm/StmP... File src/security/intel/stm/StmPlatformSmm.c:
https://review.coreboot.org/c/coreboot/+/38768/2/src/security/intel/stm/StmP... PS2, Line 165: * algorithm. (align on 4K)
My original (align on 4k) smm_save_state_size was based on the comments within Bios/StmCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c (in the STM github), lines 982-1048 and I settled on a 4K size because, in effect that was their granularity.
Heh, the comment seems to make sense, the diagram not, and the code does something entirely else (by now, of course the code was changed since the comment was written).
Can't say that I fully understand that code. Aren't SMM entries supposed to be in SMRAM? It seems they just use a standard allocator.
Obviously, I see the error of my ways. So, I look at the problem in a different manner. I look at the structure layout.
SMRAM_SAVE_STATE_MAP 0xfc00-0xffff - 0x400 SMM_PSD_OFFSET 0xfb00-0xffff - 0x100
So, the state area needs now to be increased to 0x500.
There are no requirements as to alignment, just increase the state area by 0x100, which I'll modify when I get back to my development system.
This should make it easier.
Might just work indeed. With enough space for 24 threads...
Should we work to increment SMBASE in the positive direction? Or, does that break something important?
Hmm, not sure what you are up to.