Rudolf Marek (r.marek@assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4671
-gerrit
commit 2b850eaf03649bef12dbe8098bf0382a34058739 Author: Rudolf Marek r.marek@assembler.cz Date: Sun Jan 12 00:23:30 2014 +0100
AGESA f15tn: Fix GPP ports resume
The AGESA resumes the GPP ports in the romstage using FchInitResetGpp(), which does FchGppPortInitS3Phase() for S3 resume. The PreInitGppLink() looks into CMOS to figure out what ports to just force to Gen1 or Gen2 PCIe. Then boot continues and in the ramstage the rest of GPP init is executed. There is a problem that nobody sets properly the PortDetected flags in the S3 path. As the consequence FchGppDynamicPowerSaving() thinks the GPP port is not enabled and shut downs it.
The best fix would be also to remove the CMOS dependency which might be some left over, because AGESA does not use CMOS much for anything else. There could be also some way how to pass the GPP state structure from romstage to ramstage possibly via hudson/resume.c but I don't know how to do that.
This fix fixes the resume issue on Asus F2A85-M. With this patch applied both GPP ports (used as PCIe x1 and internal ethernet) are working again after resume.
Change-Id: Idaf609043abb09441c6790504d66d23e0637588f Signed-off-by: Rudolf Marek r.marek@assembler.cz --- src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppEnv.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppEnv.c index e4db032..678ddaa 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppEnv.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppEnv.c @@ -65,10 +65,26 @@ FchInitEnvGpp ( { FCH_DATA_BLOCK *LocalCfgPtr; AMD_CONFIG_PARAMS *StdHeader; + UINT8 GppS3Data; + UINT8 PortId;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; StdHeader = LocalCfgPtr->StdHeader;
+ /* + * The romstage will force link, but re-read the GPP params from CMOS, + * otherwise the late init will powerdown all ports including + * those which were just taken out of S3 + */ + if (ReadFchSleepType (StdHeader) == ACPI_SLPTYP_S3) { + ReadMem ( ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0D, AccessWidth8, &GppS3Data); + for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) { + if ( GppS3Data & (1 << (PortId + 4))) { + LocalCfgPtr->Gpp.PortCfg[PortId].PortDetected = TRUE; + } + } + } + if ( !LocalCfgPtr->Gpp.NewGppAlgorithm) { ProgramFchGppInitReset (&LocalCfgPtr->Gpp, StdHeader); FchStall (5000, StdHeader);