Attention is currently required from: Nico Huber, Patrick Rudolph, Tim Wawrzynczak, Angel Pons, Subrata Banik. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48658 )
Change subject: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges() ......................................................................
Patch Set 3:
(5 comments)
File src/soc/intel/alderlake/espi.c:
https://review.coreboot.org/c/coreboot/+/48658/comment/154c1799_f07af6c7 PS3, Line 30: { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, : { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, : TPM_BASE_*
File src/soc/intel/apollolake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/48658/comment/547b1f02_90cf2328 PS3, Line 40: /* No TXT support. Only Locality 0 is forwared to TPM */ : #define TPM_BASE_ADDRESS 0xfed40000 : #define TPM_BASE_SIZE 0x1000 : checked with intel doc# 334818
File src/soc/intel/cannonlake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/48658/comment/38f3fbf8_335384a8 PS3, Line 24: #define TPM_BASE_ADDRESS 0xfed40000 : #define TPM_BASE_SIZE 0x8000 : checked with intel doc# 620854-002, 337867-003
File src/soc/intel/skylake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/48658/comment/95a004d3_24979965 PS3, Line 27: #define TPM_BASE_SIZE 0x8000 checked with intel doc# 332995-003EN, 332690-006EN
File src/soc/intel/xeon_sp/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/48658/comment/9097466c_bec5bc2d PS3, Line 35: #define TPM_BASE_ADDRESS 0xfed40000 : #define TPM_BASE_SIZE 0x8000 : checked with intel doc# 547817, rev1.5