Patrick Rudolph (siro@das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12893
-gerrit
commit ad7f456f9da4a6d95af230e5a0d24773d5734e03 Author: Patrick Rudolph siro@das-labor.org Date: Sat Dec 26 08:33:16 2015 +0100
intel/southbridge: move gpio.c
To change southbridge GPIOs from ram stage gpio.c has to be build. Move gpio.c into common folder to make it platform independent.
TODO: remove hardcoded GPIO code from mainboard specific code and use gpio.c.
Change-Id: Iaf0c2f941f2625a5547f9cba79da1b173da6f295 Signed-off-by: Patrick Rudolph siro@das-labor.org --- .../apple/macbookair4_2/early_southbridge.c | 2 +- src/mainboard/apple/macbookair4_2/gpio.c | 2 +- src/mainboard/getac/p470/smihandler.c | 1 + src/mainboard/gigabyte/ga-b75m-d3h/gpio.c | 2 +- src/mainboard/gigabyte/ga-b75m-d3h/romstage.c | 2 +- src/mainboard/gigabyte/ga-b75m-d3v/gpio.c | 2 +- src/mainboard/gigabyte/ga-b75m-d3v/romstage.c | 2 +- src/mainboard/google/bolt/chromeos.c | 1 + src/mainboard/google/butterfly/chromeos.c | 37 +---- src/mainboard/google/butterfly/gpio.c | 2 +- src/mainboard/google/butterfly/romstage.c | 2 +- src/mainboard/google/falco/chromeos.c | 1 + src/mainboard/google/link/gpio.h | 2 +- src/mainboard/google/link/mainboard.c | 1 + src/mainboard/google/link/romstage.c | 2 +- src/mainboard/google/panther/chromeos.c | 1 + src/mainboard/google/parrot/chromeos.c | 1 + src/mainboard/google/parrot/gpio.h | 2 +- src/mainboard/google/parrot/romstage.c | 2 +- src/mainboard/google/peppy/chromeos.c | 1 + src/mainboard/google/slippy/chromeos.c | 1 + src/mainboard/google/stout/chromeos.c | 15 +- src/mainboard/google/stout/gpio.h | 2 +- src/mainboard/google/stout/romstage.c | 2 +- src/mainboard/intel/baskingridge/chromeos.c | 24 +-- src/mainboard/intel/baskingridge/gpio.h | 2 +- src/mainboard/intel/emeraldlake2/gpio.h | 2 +- src/mainboard/intel/emeraldlake2/romstage.c | 2 +- src/mainboard/kontron/ktqm77/gpio.h | 2 +- src/mainboard/kontron/ktqm77/romstage.c | 2 +- src/mainboard/lenovo/t420s/gpio.c | 2 +- src/mainboard/lenovo/t430s/gpio.c | 2 +- src/mainboard/lenovo/t520/gpio.c | 2 +- src/mainboard/lenovo/t520/romstage.c | 2 +- src/mainboard/lenovo/t530/gpio.c | 2 +- src/mainboard/lenovo/x201/gpio.h | 2 +- src/mainboard/lenovo/x220/gpio.c | 2 +- src/mainboard/lenovo/x220/romstage.c | 2 +- src/mainboard/lenovo/x230/gpio.c | 2 +- src/mainboard/lenovo/x230/romstage.c | 2 +- src/mainboard/samsung/lumpy/chromeos.c | 10 +- src/mainboard/samsung/lumpy/gpio.h | 2 +- src/mainboard/samsung/lumpy/romstage.c | 2 +- src/mainboard/samsung/stumpy/chromeos.c | 11 +- src/mainboard/samsung/stumpy/gpio.h | 2 +- src/mainboard/samsung/stumpy/romstage.c | 2 +- src/northbridge/intel/sandybridge/romstage.c | 2 +- src/southbridge/intel/bd82x6x/Makefile.inc | 2 +- src/southbridge/intel/bd82x6x/gpio.c | 96 ----------- src/southbridge/intel/bd82x6x/gpio.h | 161 ------------------ src/southbridge/intel/bd82x6x/pch.h | 16 -- src/southbridge/intel/bd82x6x/smihandler.c | 1 + src/southbridge/intel/common/Makefile.inc | 5 + src/southbridge/intel/common/gpio.c | 158 ++++++++++++++++++ src/southbridge/intel/common/gpio.h | 183 +++++++++++++++++++++ src/southbridge/intel/i82801gx/i82801gx.h | 10 -- src/southbridge/intel/ibexpeak/Makefile.inc | 2 +- src/southbridge/intel/ibexpeak/pch.h | 16 -- src/southbridge/intel/ibexpeak/smihandler.c | 1 + src/southbridge/intel/lynxpoint/Makefile.inc | 4 - src/southbridge/intel/lynxpoint/early_pch.c | 2 +- src/southbridge/intel/lynxpoint/gpio.c | 145 ---------------- src/southbridge/intel/lynxpoint/gpio.h | 165 ------------------- src/southbridge/intel/lynxpoint/lp_gpio.h | 11 ++ src/southbridge/intel/lynxpoint/pch.h | 15 -- src/southbridge/intel/lynxpoint/pcie.c | 1 + 66 files changed, 420 insertions(+), 747 deletions(-)
diff --git a/src/mainboard/apple/macbookair4_2/early_southbridge.c b/src/mainboard/apple/macbookair4_2/early_southbridge.c index 576262d..ad78d9f 100644 --- a/src/mainboard/apple/macbookair4_2/early_southbridge.c +++ b/src/mainboard/apple/macbookair4_2/early_southbridge.c @@ -12,7 +12,7 @@ #include "northbridge/intel/sandybridge/sandybridge.h" #include "northbridge/intel/sandybridge/raminit_native.h" #include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include "southbridge/intel/common/gpio.h" #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cbfs.h> diff --git a/src/mainboard/apple/macbookair4_2/gpio.c b/src/mainboard/apple/macbookair4_2/gpio.c index 9e910b7..4d26b37 100644 --- a/src/mainboard/apple/macbookair4_2/gpio.c +++ b/src/mainboard/apple/macbookair4_2/gpio.c @@ -1,4 +1,4 @@ -#include "southbridge/intel/bd82x6x/gpio.h" +#include "southbridge/intel/common/gpio.h" const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, diff --git a/src/mainboard/getac/p470/smihandler.c b/src/mainboard/getac/p470/smihandler.c index 0dbb452..78247e8 100644 --- a/src/mainboard/getac/p470/smihandler.c +++ b/src/mainboard/getac/p470/smihandler.c @@ -19,6 +19,7 @@ #include <cpu/x86/smm.h> #include "southbridge/intel/i82801gx/i82801gx.h" #include "southbridge/intel/i82801gx/nvs.h" +#include "southbridge/intel/common/gpio.h" #include <ec/acpi/ec.h> #include "ec_oem.c"
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/gpio.c b/src/mainboard/gigabyte/ga-b75m-d3h/gpio.c index 791d7c7..fbe92da 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/gpio.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/gpio.c @@ -1,4 +1,4 @@ -#include "southbridge/intel/bd82x6x/gpio.h" +#include "southbridge/intel/common/gpio.h" static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_NATIVE, .gpio1 = GPIO_MODE_NATIVE, diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c index 8278820..9c2b2ed 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -29,7 +29,7 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/bd82x6x/gpio.h> +#include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> #include <cpu/x86/msr.h>
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/gpio.c b/src/mainboard/gigabyte/ga-b75m-d3v/gpio.c index 1f2c5e7..6244758 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/gpio.c +++ b/src/mainboard/gigabyte/ga-b75m-d3v/gpio.c @@ -1,4 +1,4 @@ -#include "southbridge/intel/bd82x6x/gpio.h" +#include "southbridge/intel/common/gpio.h" static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_NATIVE, .gpio1 = GPIO_MODE_NATIVE, diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c index b9a8c09..91fee5f 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c @@ -29,7 +29,7 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/bd82x6x/gpio.h> +#include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> #include <cpu/x86/msr.h>
diff --git a/src/mainboard/google/bolt/chromeos.c b/src/mainboard/google/bolt/chromeos.c index 2f393e0..ff0a1f7 100644 --- a/src/mainboard/google/bolt/chromeos.c +++ b/src/mainboard/google/bolt/chromeos.c @@ -19,6 +19,7 @@ #include <device/device.h> #include <device/pci.h> #include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/common/gpio.h>
#if CONFIG_EC_GOOGLE_CHROMEEC #include "ec.h" diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 0b750b1..69887f5 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -21,6 +21,7 @@ #include <device/pci.h>
#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> #include <ec/quanta/ene_kb3940q/ec.h> #include "ec.h"
@@ -29,9 +30,6 @@ #define FORCE_RECOVERY_MODE 0 #define FORCE_DEVELOPER_MODE 0
- -int get_pch_gpio(unsigned char gpio_num); - #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h>
@@ -92,38 +90,9 @@ void fill_lb_gpios(struct lb_gpios *gpios) } #endif
-int get_pch_gpio(unsigned char gpio_num) -{ - device_t dev; - int retval = 0; - -#ifdef __PRE_RAM__ - dev = PCI_DEV(0, 0x1f, 0); -#else - dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); -#endif - u16 gpio_base = pci_read_config16(dev, GPIOBASE) & 0xfffe; - - if (!gpio_base) - return(0); - - if (gpio_num >= 64){ - u32 gp_lvl3 = inl(gpio_base + GP_LVL3); - retval = ((gp_lvl3 >> (gpio_num - 64)) & 1); - } else if (gpio_num >= 32){ - u32 gp_lvl2 = inl(gpio_base + GP_LVL2); - retval = ((gp_lvl2 >> (gpio_num - 32)) & 1); - } else { - u32 gp_lvl = inl(gpio_base + GP_LVL); - retval = ((gp_lvl >> gpio_num) & 1); - } - - return retval; -} - int get_write_protect_state(void) { - return !get_pch_gpio(WP_GPIO); + return !get_gpio(WP_GPIO); }
int get_lid_switch(void) @@ -141,7 +110,7 @@ int get_developer_mode_switch(void) #endif
/* Servo GPIO is active low, reverse it for intial state (request) */ - dev_mode = !get_pch_gpio(DEVMODE_GPIO); + dev_mode = !get_gpio(DEVMODE_GPIO); printk(BIOS_DEBUG,"DEVELOPER MODE FROM GPIO %d: %x\n",DEVMODE_GPIO, dev_mode);
diff --git a/src/mainboard/google/butterfly/gpio.c b/src/mainboard/google/butterfly/gpio.c index a08b787..2357373 100644 --- a/src/mainboard/google/butterfly/gpio.c +++ b/src/mainboard/google/butterfly/gpio.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */
-#include "southbridge/intel/bd82x6x/gpio.h" +#include "southbridge/intel/common/gpio.h"
const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_NONE, /* Unused */ diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 6b7562d..ceb98f5 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -29,7 +29,7 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/bd82x6x/gpio.h> +#include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <halt.h> diff --git a/src/mainboard/google/falco/chromeos.c b/src/mainboard/google/falco/chromeos.c index a7d96a8..f0e6a5a 100644 --- a/src/mainboard/google/falco/chromeos.c +++ b/src/mainboard/google/falco/chromeos.c @@ -19,6 +19,7 @@ #include <device/device.h> #include <device/pci.h> #include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/common/gpio.h>
#if CONFIG_EC_GOOGLE_CHROMEEC #include "ec.h" diff --git a/src/mainboard/google/link/gpio.h b/src/mainboard/google/link/gpio.h index 1dab97e..9bdccd5 100644 --- a/src/mainboard/google/link/gpio.h +++ b/src/mainboard/google/link/gpio.h @@ -16,7 +16,7 @@ #ifndef LINK_GPIO_H #define LINK_GPIO_H
-#include "southbridge/intel/bd82x6x/gpio.h" +#include "southbridge/intel/common/gpio.h"
const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, /* NMI_DBG# */ diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index 3e241d4..0a1c9f0 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -32,6 +32,7 @@ #include "onboard.h" #include "ec.h" #include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> #include <smbios.h> #include <device/pci.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index a0970df..fe24adc 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -30,7 +30,7 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/bd82x6x/gpio.h> +#include <southbridge/intel/common/gpio.h> #include "ec/google/chromeec/ec.h" #include <arch/cpu.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/google/panther/chromeos.c b/src/mainboard/google/panther/chromeos.c index 2c5c234..17917b1 100644 --- a/src/mainboard/google/panther/chromeos.c +++ b/src/mainboard/google/panther/chromeos.c @@ -19,6 +19,7 @@ #include <device/device.h> #include <device/pci.h> #include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h>
#define GPIO_SPI_WP 58 diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 82198a9..5f190bc 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -21,6 +21,7 @@ #include <device/pci.h>
#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> #include <ec/compal/ene932/ec.h> #include "ec.h"
diff --git a/src/mainboard/google/parrot/gpio.h b/src/mainboard/google/parrot/gpio.h index 1cfd487..bd30719 100644 --- a/src/mainboard/google/parrot/gpio.h +++ b/src/mainboard/google/parrot/gpio.h @@ -16,7 +16,7 @@ #ifndef PARROT_GPIO_H #define PARROT_GPIO_H
-#include "southbridge/intel/bd82x6x/gpio.h" +#include "southbridge/intel/common/gpio.h"
const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_NONE, /* NOT USED */ diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 029805b..773704c 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -29,7 +29,7 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/bd82x6x/gpio.h> +#include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/google/peppy/chromeos.c b/src/mainboard/google/peppy/chromeos.c index a7d96a8..f0e6a5a 100644 --- a/src/mainboard/google/peppy/chromeos.c +++ b/src/mainboard/google/peppy/chromeos.c @@ -19,6 +19,7 @@ #include <device/device.h> #include <device/pci.h> #include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/common/gpio.h>
#if CONFIG_EC_GOOGLE_CHROMEEC #include "ec.h" diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index a7d96a8..f0e6a5a 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -19,6 +19,7 @@ #include <device/device.h> #include <device/pci.h> #include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/common/gpio.h>
#if CONFIG_EC_GOOGLE_CHROMEEC #include "ec.h" diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index a2abaed..5fc83fb 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -81,20 +81,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_write_protect_state(void) { - device_t dev; -#ifdef __PRE_RAM__ - dev = PCI_DEV(0, 0x1f, 0); -#else - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); -#endif - u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe; - - if (!gpio_base) - return 0; - - u32 gp_lvl = inl(gpio_base + GP_LVL); - - return !((gp_lvl >> 7) & 1); + return !get_gpio(7); }
int get_lid_switch(void) diff --git a/src/mainboard/google/stout/gpio.h b/src/mainboard/google/stout/gpio.h index f992013..5d69f9b 100644 --- a/src/mainboard/google/stout/gpio.h +++ b/src/mainboard/google/stout/gpio.h @@ -16,7 +16,7 @@ #ifndef STOUT_GPIO_H #define STOUT_GPIO_H
-#include "southbridge/intel/bd82x6x/gpio.h" +#include "southbridge/intel/common/gpio.h"
const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, /* GPIO0 */ diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 030dee7..f6ce977 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -29,7 +29,7 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/bd82x6x/gpio.h> +#include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 3885257..94e8d89 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -19,7 +19,7 @@ #include <device/device.h> #include <device/pci.h> #include <southbridge/intel/lynxpoint/pch.h> -#include <southbridge/intel/lynxpoint/gpio.h> +#include <southbridge/intel/common/gpio.h>
#ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> @@ -82,38 +82,20 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_developer_mode_switch(void) { - device_t dev; -#ifdef __PRE_RAM__ - dev = PCI_DEV(0, 0x1f, 0); -#else - dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); -#endif - u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe; - u32 gp_lvl2 = inl(gpio_base + GP_LVL2); - /* * Developer: GPIO48, Connected to J8E4, however the silkscreen says * J8E3. The jumper is active low. */ - return !((gp_lvl2 >> (48-32)) & 1); + return !get_gpio(48); }
int get_recovery_mode_switch(void) { - device_t dev; -#ifdef __PRE_RAM__ - dev = PCI_DEV(0, 0x1f, 0); -#else - dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); -#endif - u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe; - u32 gp_lvl3 = inl(gpio_base + GP_LVL3); - /* * Recovery: GPIO69, Connected to J8E3, however the silkscreen says * J8E2. The jump is active high. */ - return (gp_lvl3 >> (69-64)) & 1; + return get_gpio(69); }
int get_write_protect_state(void) diff --git a/src/mainboard/intel/baskingridge/gpio.h b/src/mainboard/intel/baskingridge/gpio.h index 99bec38..0f519c5 100644 --- a/src/mainboard/intel/baskingridge/gpio.h +++ b/src/mainboard/intel/baskingridge/gpio.h @@ -16,7 +16,7 @@ #ifndef BASKING_RIDGE_GPIO_H #define BASKING_RIDGE_GPIO_H
-#include "southbridge/intel/lynxpoint/gpio.h" +#include "southbridge/intel/common/gpio.h"
const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, /* PCH_GPIO0_R -> S_GPIO -> J9F4 */ diff --git a/src/mainboard/intel/emeraldlake2/gpio.h b/src/mainboard/intel/emeraldlake2/gpio.h index 81bccdf..6dbb5aa 100644 --- a/src/mainboard/intel/emeraldlake2/gpio.h +++ b/src/mainboard/intel/emeraldlake2/gpio.h @@ -16,7 +16,7 @@ #ifndef EMERALDLAKE2_GPIO_H #define EMERALDLAKE2_GPIO_H
-#include "southbridge/intel/bd82x6x/gpio.h" +#include "southbridge/intel/common/gpio.h"
const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 5cf24b2..7eba3da 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -30,7 +30,7 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/bd82x6x/gpio.h> +#include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/kontron/ktqm77/gpio.h b/src/mainboard/kontron/ktqm77/gpio.h index 23139f7..01c5b8f 100644 --- a/src/mainboard/kontron/ktqm77/gpio.h +++ b/src/mainboard/kontron/ktqm77/gpio.h @@ -16,7 +16,7 @@ #ifndef KTQM77_GPIO_H #define KTQM77_GPIO_H
-#include "southbridge/intel/bd82x6x/gpio.h" +#include "southbridge/intel/common/gpio.h"
/* * TODO: Investigate somehow... Current values are taken from a running diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 4a9efa6..6d8cf4a 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -29,7 +29,7 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/bd82x6x/gpio.h> +#include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/lenovo/t420s/gpio.c b/src/mainboard/lenovo/t420s/gpio.c index 14dee2d..4ed31fe 100644 --- a/src/mainboard/lenovo/t420s/gpio.c +++ b/src/mainboard/lenovo/t420s/gpio.c @@ -1,4 +1,4 @@ -#include "southbridge/intel/bd82x6x/gpio.h" +#include "southbridge/intel/common/gpio.h" const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, // -USB30_SMIB - input .gpio1 = GPIO_MODE_GPIO, // -EC_SCI - input diff --git a/src/mainboard/lenovo/t430s/gpio.c b/src/mainboard/lenovo/t430s/gpio.c index a1c345c..38096a6 100644 --- a/src/mainboard/lenovo/t430s/gpio.c +++ b/src/mainboard/lenovo/t430s/gpio.c @@ -1,4 +1,4 @@ -#include "southbridge/intel/bd82x6x/gpio.h" +#include "southbridge/intel/common/gpio.h" const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, // -EC_SCI - input diff --git a/src/mainboard/lenovo/t520/gpio.c b/src/mainboard/lenovo/t520/gpio.c index 9412ef9..1b1760c 100644 --- a/src/mainboard/lenovo/t520/gpio.c +++ b/src/mainboard/lenovo/t520/gpio.c @@ -16,7 +16,7 @@ #ifndef T520_GPIO_H #define T520_GPIO_H
-#include "southbridge/intel/bd82x6x/gpio.h" +#include "southbridge/intel/common/gpio.h"
const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, // -USB30_SMI - input diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index eb1d0cf..60861a5 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -31,7 +31,7 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/bd82x6x/gpio.h> +#include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cbfs.h> diff --git a/src/mainboard/lenovo/t530/gpio.c b/src/mainboard/lenovo/t530/gpio.c index 32e0e17..fe02c1d 100644 --- a/src/mainboard/lenovo/t530/gpio.c +++ b/src/mainboard/lenovo/t530/gpio.c @@ -1,4 +1,4 @@ -#include "southbridge/intel/bd82x6x/gpio.h" +#include "southbridge/intel/common/gpio.h" const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, diff --git a/src/mainboard/lenovo/x201/gpio.h b/src/mainboard/lenovo/x201/gpio.h index 914d0ad..cc73423 100644 --- a/src/mainboard/lenovo/x201/gpio.h +++ b/src/mainboard/lenovo/x201/gpio.h @@ -16,7 +16,7 @@ #ifndef LENOVO_X201_GPIO_H #define LENOVO_X201_GPIO_H
-#include "southbridge/intel/bd82x6x/gpio.h" +#include "southbridge/intel/common/gpio.h"
const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, diff --git a/src/mainboard/lenovo/x220/gpio.c b/src/mainboard/lenovo/x220/gpio.c index 13cfa7d..1db535a 100644 --- a/src/mainboard/lenovo/x220/gpio.c +++ b/src/mainboard/lenovo/x220/gpio.c @@ -1,4 +1,4 @@ -#include "southbridge/intel/bd82x6x/gpio.h" +#include "southbridge/intel/common/gpio.h" static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index 1d89d92..9d6c33c 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -29,7 +29,7 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/bd82x6x/gpio.h> +#include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> #include <cpu/x86/msr.h>
diff --git a/src/mainboard/lenovo/x230/gpio.c b/src/mainboard/lenovo/x230/gpio.c index 6570018..d5c8e97 100644 --- a/src/mainboard/lenovo/x230/gpio.c +++ b/src/mainboard/lenovo/x230/gpio.c @@ -17,7 +17,7 @@ #ifndef X230_GPIO_H #define X230_GPIO_H
-#include "southbridge/intel/bd82x6x/gpio.h" +#include "southbridge/intel/common/gpio.h"
const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 316e51d..abfc3b7 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -31,7 +31,7 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/bd82x6x/gpio.h> +#include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cbfs.h> diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index 4bf6968..9ee32bb 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -20,6 +20,7 @@ #include <device/pci.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h>
#define GPIO_SPI_WP 24 #define GPIO_REC_MODE 42 @@ -119,19 +120,16 @@ int get_recovery_mode_switch(void) void init_bootmode_straps(void) { #ifdef __PRE_RAM__ - u16 gpio_base = pci_read_config32(PCH_LPC_DEV, GPIO_BASE) & 0xfffe; - u32 gp_lvl2 = inl(gpio_base + GP_LVL2); - u32 gp_lvl = inl(gpio_base + GP_LVL); u32 flags = 0;
/* Write Protect: GPIO24 = KBC3_SPI_WP#, active high */ - if (gp_lvl & (1 << GPIO_SPI_WP)) + if (get_gpio(GPIO_SPI_WP)) flags |= (1 << FLAG_SPI_WP); /* Recovery: GPIO42 = CHP3_REC_MODE#, active low */ - if (!(gp_lvl2 & (1 << (GPIO_REC_MODE-32)))) + if (!get_gpio(GPIO_REC_MODE)) flags |= (1 << FLAG_REC_MODE); /* Developer: GPIO17 = KBC3_DVP_MODE, active high */ - if (gp_lvl & (1 << GPIO_DEV_MODE)) + if (get_gpio(GPIO_DEV_MODE)) flags |= (1 << FLAG_DEV_MODE);
pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); diff --git a/src/mainboard/samsung/lumpy/gpio.h b/src/mainboard/samsung/lumpy/gpio.h index 58b61b6..f9937c9 100644 --- a/src/mainboard/samsung/lumpy/gpio.h +++ b/src/mainboard/samsung/lumpy/gpio.h @@ -16,7 +16,7 @@ #ifndef LUMPY_GPIO_H #define LUMPY_GPIO_H
-#include "southbridge/intel/bd82x6x/gpio.h" +#include "southbridge/intel/common/gpio.h"
/* * GPIO SET 1 includes GPIO0 to GPIO31 diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 5f37583..a54a285 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -32,7 +32,7 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/bd82x6x/gpio.h> +#include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 8b6716a..5f2a062 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -19,6 +19,7 @@ #include <device/device.h> #include <device/pci.h> #include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h>
#define GPIO_SPI_WP 68 #define GPIO_REC_MODE 42 @@ -116,20 +117,16 @@ int get_recovery_mode_switch(void) void init_bootmode_straps(void) { #ifdef __PRE_RAM__ - u16 gpio_base = pci_read_config32(PCH_LPC_DEV, GPIO_BASE) & 0xfffe; - u32 gp_lvl3 = inl(gpio_base + GP_LVL3); - u32 gp_lvl2 = inl(gpio_base + GP_LVL2); - u32 gp_lvl = inl(gpio_base + GP_LVL); u32 flags = 0;
/* Write Protect: GPIO68 = CHP3_SPI_WP, active high */ - if (gp_lvl3 & (1 << (GPIO_SPI_WP-64))) + if (get_gpio(GPIO_SPI_WP)) flags |= (1 << FLAG_SPI_WP); /* Recovery: GPIO42 = CHP3_REC_MODE#, active low */ - if (!(gp_lvl2 & (1 << (GPIO_REC_MODE-32)))) + if (!get_gpio(GPIO_REC_MODE)) flags |= (1 << FLAG_REC_MODE); /* Developer: GPIO17 = KBC3_DVP_MODE, active high */ - if (gp_lvl & (1 << GPIO_DEV_MODE)) + if (get_gpio(GPIO_DEV_MODE)) flags |= (1 << FLAG_DEV_MODE);
pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); diff --git a/src/mainboard/samsung/stumpy/gpio.h b/src/mainboard/samsung/stumpy/gpio.h index 74d095b..fd7b8ef 100644 --- a/src/mainboard/samsung/stumpy/gpio.h +++ b/src/mainboard/samsung/stumpy/gpio.h @@ -16,7 +16,7 @@ #ifndef STUMPY_GPIO_H #define STUMPY_GPIO_H
-#include "southbridge/intel/bd82x6x/gpio.h" +#include "southbridge/intel/common/gpio.h"
/* * GPIO SET 1 includes GPIO0 to GPIO31 diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index bf1ddb3..145b2e0 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -32,7 +32,7 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/bd82x6x/gpio.h> +#include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 34d759f..915fe24 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -32,7 +32,7 @@ #include "raminit_native.h" #include <northbridge/intel/sandybridge/chip.h> #include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include "southbridge/intel/common/gpio.h"
#define HOST_BRIDGE PCI_DEVFN(0, 0) #define DEFAULT_TCK TCK_800MHZ diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index a8dd7be..24c0de9 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -41,7 +41,7 @@ smm-$(CONFIG_SPI_FLASH_SMM) += ../common/spi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c pch.c
-romstage-y += early_smbus.c me_status.c gpio.c +romstage-y += early_smbus.c me_status.c romstage-y += reset.c romstage-y += early_spi.c early_pch_common.c romstage-y += early_rcba.c diff --git a/src/southbridge/intel/bd82x6x/gpio.c b/src/southbridge/intel/bd82x6x/gpio.c deleted file mode 100644 index 6624156..0000000 --- a/src/southbridge/intel/bd82x6x/gpio.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <arch/io.h> - -#include "pch.h" -#include "gpio.h" - -#define MAX_GPIO_NUMBER 75 /* zero based */ - -void setup_pch_gpios(const struct pch_gpio_map *gpio) -{ - u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; - - /* GPIO Set 1 */ - if (gpio->set1.level) - outl(*((u32*)gpio->set1.level), gpiobase + GP_LVL); - if (gpio->set1.mode) - outl(*((u32*)gpio->set1.mode), gpiobase + GPIO_USE_SEL); - if (gpio->set1.direction) - outl(*((u32*)gpio->set1.direction), gpiobase + GP_IO_SEL); - if (gpio->set1.reset) - outl(*((u32*)gpio->set1.reset), gpiobase + GP_RST_SEL1); - if (gpio->set1.invert) - outl(*((u32*)gpio->set1.invert), gpiobase + GPI_INV); - if (gpio->set1.blink) - outl(*((u32*)gpio->set1.blink), gpiobase + GPO_BLINK); - - /* GPIO Set 2 */ - if (gpio->set2.level) - outl(*((u32*)gpio->set2.level), gpiobase + GP_LVL2); - if (gpio->set2.mode) - outl(*((u32*)gpio->set2.mode), gpiobase + GPIO_USE_SEL2); - if (gpio->set2.direction) - outl(*((u32*)gpio->set2.direction), gpiobase + GP_IO_SEL2); - if (gpio->set2.reset) - outl(*((u32*)gpio->set2.reset), gpiobase + GP_RST_SEL2); - - /* GPIO Set 3 */ - if (gpio->set3.level) - outl(*((u32*)gpio->set3.level), gpiobase + GP_LVL3); - if (gpio->set3.mode) - outl(*((u32*)gpio->set3.mode), gpiobase + GPIO_USE_SEL3); - if (gpio->set3.direction) - outl(*((u32*)gpio->set3.direction), gpiobase + GP_IO_SEL3); - if (gpio->set3.reset) - outl(*((u32*)gpio->set3.reset), gpiobase + GP_RST_SEL3); -} - -int get_gpio(int gpio_num) -{ - static const int gpio_reg_offsets[] = {0xc, 0x38, 0x48}; - u16 gpio_base = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; - int index, bit; - - if (gpio_num > MAX_GPIO_NUMBER) - return 0; /* Just ignore wrong gpio numbers. */ - - index = gpio_num / 32; - bit = gpio_num % 32; - - return (inl(gpio_base + gpio_reg_offsets[index]) >> bit) & 1; -} - -/* - * get a number comprised of multiple GPIO values. gpio_num_array points to - * the array of gpio pin numbers to scan, terminated by -1. - */ -unsigned get_gpios(const int *gpio_num_array) -{ - int gpio; - unsigned bitmask = 1; - unsigned vector = 0; - - while (bitmask && - ((gpio = *gpio_num_array++) != -1)) { - if (get_gpio(gpio)) - vector |= bitmask; - bitmask <<= 1; - } - return vector; -} diff --git a/src/southbridge/intel/bd82x6x/gpio.h b/src/southbridge/intel/bd82x6x/gpio.h deleted file mode 100644 index a0aefe8..0000000 --- a/src/southbridge/intel/bd82x6x/gpio.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef INTEL_BD82X6X_GPIO_H -#define INTEL_BD82X6X_GPIO_H - -#include <stdint.h> - -#define GPIO_MODE_NATIVE 0 -#define GPIO_MODE_GPIO 1 -#define GPIO_MODE_NONE 1 - -#define GPIO_DIR_OUTPUT 0 -#define GPIO_DIR_INPUT 1 - -#define GPIO_NO_INVERT 0 -#define GPIO_INVERT 1 - -#define GPIO_LEVEL_LOW 0 -#define GPIO_LEVEL_HIGH 1 - -#define GPIO_NO_BLINK 0 -#define GPIO_BLINK 1 - -#define GPIO_RESET_PWROK 0 -#define GPIO_RESET_RSMRST 1 - -struct pch_gpio_set1 { - u32 gpio0 : 1; - u32 gpio1 : 1; - u32 gpio2 : 1; - u32 gpio3 : 1; - u32 gpio4 : 1; - u32 gpio5 : 1; - u32 gpio6 : 1; - u32 gpio7 : 1; - u32 gpio8 : 1; - u32 gpio9 : 1; - u32 gpio10 : 1; - u32 gpio11 : 1; - u32 gpio12 : 1; - u32 gpio13 : 1; - u32 gpio14 : 1; - u32 gpio15 : 1; - u32 gpio16 : 1; - u32 gpio17 : 1; - u32 gpio18 : 1; - u32 gpio19 : 1; - u32 gpio20 : 1; - u32 gpio21 : 1; - u32 gpio22 : 1; - u32 gpio23 : 1; - u32 gpio24 : 1; - u32 gpio25 : 1; - u32 gpio26 : 1; - u32 gpio27 : 1; - u32 gpio28 : 1; - u32 gpio29 : 1; - u32 gpio30 : 1; - u32 gpio31 : 1; -} __attribute__ ((packed)); - -struct pch_gpio_set2 { - u32 gpio32 : 1; - u32 gpio33 : 1; - u32 gpio34 : 1; - u32 gpio35 : 1; - u32 gpio36 : 1; - u32 gpio37 : 1; - u32 gpio38 : 1; - u32 gpio39 : 1; - u32 gpio40 : 1; - u32 gpio41 : 1; - u32 gpio42 : 1; - u32 gpio43 : 1; - u32 gpio44 : 1; - u32 gpio45 : 1; - u32 gpio46 : 1; - u32 gpio47 : 1; - u32 gpio48 : 1; - u32 gpio49 : 1; - u32 gpio50 : 1; - u32 gpio51 : 1; - u32 gpio52 : 1; - u32 gpio53 : 1; - u32 gpio54 : 1; - u32 gpio55 : 1; - u32 gpio56 : 1; - u32 gpio57 : 1; - u32 gpio58 : 1; - u32 gpio59 : 1; - u32 gpio60 : 1; - u32 gpio61 : 1; - u32 gpio62 : 1; - u32 gpio63 : 1; -} __attribute__ ((packed)); - -struct pch_gpio_set3 { - u32 gpio64 : 1; - u32 gpio65 : 1; - u32 gpio66 : 1; - u32 gpio67 : 1; - u32 gpio68 : 1; - u32 gpio69 : 1; - u32 gpio70 : 1; - u32 gpio71 : 1; - u32 gpio72 : 1; - u32 gpio73 : 1; - u32 gpio74 : 1; - u32 gpio75 : 1; -} __attribute__ ((packed)); - -struct pch_gpio_map { - struct { - const struct pch_gpio_set1 *mode; - const struct pch_gpio_set1 *direction; - const struct pch_gpio_set1 *level; - const struct pch_gpio_set1 *reset; - const struct pch_gpio_set1 *invert; - const struct pch_gpio_set1 *blink; - } set1; - struct { - const struct pch_gpio_set2 *mode; - const struct pch_gpio_set2 *direction; - const struct pch_gpio_set2 *level; - const struct pch_gpio_set2 *reset; - } set2; - struct { - const struct pch_gpio_set3 *mode; - const struct pch_gpio_set3 *direction; - const struct pch_gpio_set3 *level; - const struct pch_gpio_set3 *reset; - } set3; -}; - -extern const struct pch_gpio_map mainboard_gpio_map; - -/* Configure GPIOs with mainboard provided settings */ -void setup_pch_gpios(const struct pch_gpio_map *gpio); - -/* get GPIO pin value */ -int get_gpio(int gpio_num); -/* - * get a number comprised of multiple GPIO values. gpio_num_array points to - * the array of gpio pin numbers to scan, terminated by -1. - */ -unsigned get_gpios(const int *gpio_num_array); - -#endif diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index ba4391d..b30c48c 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -462,22 +462,6 @@ early_usb_init (const struct southbridge_usb_port *portmap); #define XUSB2PRM 0xd4 /* 32bit */ #define USB3PRM 0xdc /* 32bit */
-/* ICH7 GPIOBASE */ -#define GPIO_USE_SEL 0x00 -#define GP_IO_SEL 0x04 -#define GP_LVL 0x0c -#define GPO_BLINK 0x18 -#define GPI_INV 0x2c -#define GPIO_USE_SEL2 0x30 -#define GP_IO_SEL2 0x34 -#define GP_LVL2 0x38 -#define GPIO_USE_SEL3 0x40 -#define GP_IO_SEL3 0x44 -#define GP_LVL3 0x48 -#define GP_RST_SEL1 0x60 -#define GP_RST_SEL2 0x64 -#define GP_RST_SEL3 0x68 - /* ICH7 PMBASE */ #define PM1_STS 0x00 #define WAK_STS (1 << 15) diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index f6fbac3..4948616 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -30,6 +30,7 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <arch/pci_mmio_cfg.h> #include <southbridge/intel/bd82x6x/me.h> +#include <southbridge/intel/common/gpio.h> #include <cpu/intel/model_206ax/model_206ax.h>
/* While we read PMBASE dynamically in case it changed, let's diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 513f288..5bfd0a1 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -21,4 +21,9 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y) romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += usb_debug.c ramstage-$(CONFIG_USBDEBUG) += usb_debug.c
+ifneq ($(CONFIG_INTEL_LYNXPOINT_LP),y) +romstage-y += gpio.c +ramstage-y += gpio.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += gpio.c +endif endif diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c new file mode 100644 index 0000000..9ce66ed --- /dev/null +++ b/src/southbridge/intel/common/gpio.c @@ -0,0 +1,158 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2016 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> + +#include "gpio.h" + +#define MAX_GPIO_NUMBER 75 /* zero based */ + +/* LPC GPIO Base Address Register */ +#define GPIO_BASE 0x48 +/* PCI Configuration Space (D31:F0): LPC */ +#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) + +static u16 get_gpio_base(void) +{ +#if defined(__PRE_RAM__) || defined(__SMM__) + return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; +#else + return pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), + GPIO_BASE) & 0xfffc; +#endif +} + +void setup_pch_gpios(const struct pch_gpio_map *gpio) +{ + u16 gpiobase = get_gpio_base(); + + /* GPIO Set 1 */ + if (gpio->set1.level) + outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL); + if (gpio->set1.mode) + outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL); + if (gpio->set1.direction) + outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL); + if (gpio->set1.reset) + outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1); + if (gpio->set1.invert) + outl(*((u32 *)gpio->set1.invert), gpiobase + GPI_INV); + if (gpio->set1.blink) + outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK); + + /* GPIO Set 2 */ + if (gpio->set2.level) + outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2); + if (gpio->set2.mode) + outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2); + if (gpio->set2.direction) + outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2); + if (gpio->set2.reset) + outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2); + + /* GPIO Set 3 */ + if (gpio->set3.level) + outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3); + if (gpio->set3.mode) + outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3); + if (gpio->set3.direction) + outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3); + if (gpio->set3.reset) + outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3); +} + +/* + * return current gpio level. + */ +int get_gpio(int gpio_num) +{ + static const int gpio_reg_offsets[] = {GP_LVL, GP_LVL2, GP_LVL3}; + u16 gpio_base = get_gpio_base(); + int index, bit; + + if (gpio_num > MAX_GPIO_NUMBER) + return 0; /* Just ignore wrong gpio numbers. */ + + index = gpio_num / 32; + bit = gpio_num % 32; + + return (inl(gpio_base + gpio_reg_offsets[index]) >> bit) & 1; +} + +/* + * get a number comprised of multiple GPIO values. gpio_num_array points to + * the array of gpio pin numbers to scan, terminated by -1. + */ +unsigned get_gpios(const int *gpio_num_array) +{ + int gpio; + unsigned bitmask = 1; + unsigned vector = 0; + + while (bitmask && + ((gpio = *gpio_num_array++) != -1)) { + if (get_gpio(gpio)) + vector |= bitmask; + bitmask <<= 1; + } + return vector; +} + +/* + * set gpio output to level. + */ +void set_gpio(int gpio_num, int value) +{ + static const int gpio_reg_offsets[] = { + GP_LVL, GP_LVL2, GP_LVL3 + }; + u16 gpio_base = get_gpio_base(); + int index, bit; + u32 config; + + if (gpio_num > MAX_GPIO_NUMBER) + return; /* Just ignore wrong gpio numbers. */ + + index = gpio_num / 32; + bit = gpio_num % 32; + + config = inl(gpio_base + gpio_reg_offsets[index]); + config &= ~(1 << bit); + config |= value << bit; + outl(config, gpio_base + gpio_reg_offsets[index]); +} + +int gpio_is_native(int gpio_num) +{ + static const int gpio_reg_offsets[] = { + GPIO_USE_SEL, GPIO_USE_SEL2, GPIO_USE_SEL3 + }; + u16 gpio_base = get_gpio_base(); + int index, bit; + u32 config; + + if (gpio_num > MAX_GPIO_NUMBER) + return 0; /* Just ignore wrong gpio numbers. */ + + index = gpio_num / 32; + bit = gpio_num % 32; + + config = inl(gpio_base + gpio_reg_offsets[index]); + return !(config & (1 << bit)); +} diff --git a/src/southbridge/intel/common/gpio.h b/src/southbridge/intel/common/gpio.h new file mode 100644 index 0000000..0067918 --- /dev/null +++ b/src/southbridge/intel/common/gpio.h @@ -0,0 +1,183 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2016 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef INTEL_BD82X6X_GPIO_H +#define INTEL_BD82X6X_GPIO_H + +#include <stdint.h> + +/* ICH7 GPIOBASE */ +#define GPIO_USE_SEL 0x00 +#define GP_IO_SEL 0x04 +#define GP_LVL 0x0c +#define GPO_BLINK 0x18 +#define GPI_INV 0x2c +#define GPIO_USE_SEL2 0x30 +#define GP_IO_SEL2 0x34 +#define GP_LVL2 0x38 +#define GPIO_USE_SEL3 0x40 +#define GP_IO_SEL3 0x44 +#define GP_LVL3 0x48 +#define GP_RST_SEL1 0x60 +#define GP_RST_SEL2 0x64 +#define GP_RST_SEL3 0x68 + +#define GPIO_MODE_NATIVE 0 +#define GPIO_MODE_GPIO 1 +#define GPIO_MODE_NONE 1 + +#define GPIO_DIR_OUTPUT 0 +#define GPIO_DIR_INPUT 1 + +#define GPIO_NO_INVERT 0 +#define GPIO_INVERT 1 + +#define GPIO_LEVEL_LOW 0 +#define GPIO_LEVEL_HIGH 1 + +#define GPIO_NO_BLINK 0 +#define GPIO_BLINK 1 + +#define GPIO_RESET_PWROK 0 +#define GPIO_RESET_RSMRST 1 + +struct pch_gpio_set1 { + u32 gpio0 : 1; + u32 gpio1 : 1; + u32 gpio2 : 1; + u32 gpio3 : 1; + u32 gpio4 : 1; + u32 gpio5 : 1; + u32 gpio6 : 1; + u32 gpio7 : 1; + u32 gpio8 : 1; + u32 gpio9 : 1; + u32 gpio10 : 1; + u32 gpio11 : 1; + u32 gpio12 : 1; + u32 gpio13 : 1; + u32 gpio14 : 1; + u32 gpio15 : 1; + u32 gpio16 : 1; + u32 gpio17 : 1; + u32 gpio18 : 1; + u32 gpio19 : 1; + u32 gpio20 : 1; + u32 gpio21 : 1; + u32 gpio22 : 1; + u32 gpio23 : 1; + u32 gpio24 : 1; + u32 gpio25 : 1; + u32 gpio26 : 1; + u32 gpio27 : 1; + u32 gpio28 : 1; + u32 gpio29 : 1; + u32 gpio30 : 1; + u32 gpio31 : 1; +} __attribute__ ((packed)); + +struct pch_gpio_set2 { + u32 gpio32 : 1; + u32 gpio33 : 1; + u32 gpio34 : 1; + u32 gpio35 : 1; + u32 gpio36 : 1; + u32 gpio37 : 1; + u32 gpio38 : 1; + u32 gpio39 : 1; + u32 gpio40 : 1; + u32 gpio41 : 1; + u32 gpio42 : 1; + u32 gpio43 : 1; + u32 gpio44 : 1; + u32 gpio45 : 1; + u32 gpio46 : 1; + u32 gpio47 : 1; + u32 gpio48 : 1; + u32 gpio49 : 1; + u32 gpio50 : 1; + u32 gpio51 : 1; + u32 gpio52 : 1; + u32 gpio53 : 1; + u32 gpio54 : 1; + u32 gpio55 : 1; + u32 gpio56 : 1; + u32 gpio57 : 1; + u32 gpio58 : 1; + u32 gpio59 : 1; + u32 gpio60 : 1; + u32 gpio61 : 1; + u32 gpio62 : 1; + u32 gpio63 : 1; +} __attribute__ ((packed)); + +struct pch_gpio_set3 { + u32 gpio64 : 1; + u32 gpio65 : 1; + u32 gpio66 : 1; + u32 gpio67 : 1; + u32 gpio68 : 1; + u32 gpio69 : 1; + u32 gpio70 : 1; + u32 gpio71 : 1; + u32 gpio72 : 1; + u32 gpio73 : 1; + u32 gpio74 : 1; + u32 gpio75 : 1; +} __attribute__ ((packed)); + +struct pch_gpio_map { + struct { + const struct pch_gpio_set1 *mode; + const struct pch_gpio_set1 *direction; + const struct pch_gpio_set1 *level; + const struct pch_gpio_set1 *reset; + const struct pch_gpio_set1 *invert; + const struct pch_gpio_set1 *blink; + } set1; + struct { + const struct pch_gpio_set2 *mode; + const struct pch_gpio_set2 *direction; + const struct pch_gpio_set2 *level; + const struct pch_gpio_set2 *reset; + } set2; + struct { + const struct pch_gpio_set3 *mode; + const struct pch_gpio_set3 *direction; + const struct pch_gpio_set3 *level; + const struct pch_gpio_set3 *reset; + } set3; +}; + +extern const struct pch_gpio_map mainboard_gpio_map; + +/* Configure GPIOs with mainboard provided settings */ +void setup_pch_gpios(const struct pch_gpio_map *gpio); + +/* get GPIO pin value */ +int get_gpio(int gpio_num); +/* + * get a number comprised of multiple GPIO values. gpio_num_array points to + * the array of gpio pin numbers to scan, terminated by -1. + */ +unsigned get_gpios(const int *gpio_num_array); + +void set_gpio(int gpio_num, int value); + +void clear_gpio(int gpio_num); + +int gpio_is_native(int gpio_num); + +#endif diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 35297c7..17b7026 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -302,16 +302,6 @@ int southbridge_detect_s3_resume(void); #define FD_SATA (1 << 2) #define FD_PATA (1 << 1)
-/* ICH7 GPIOBASE */ -#define GPIO_USE_SEL 0x00 -#define GP_IO_SEL 0x04 -#define GP_LVL 0x0c -#define GPO_BLINK 0x18 -#define GPI_INV 0x2c -#define GPIO_USE_SEL2 0x30 -#define GP_IO_SEL2 0x34 -#define GP_LVL2 0x38 - /* ICH7 PMBASE */ #define PM1_STS 0x00 #define WAK_STS (1 << 15) diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index 2987ea9..41d3afb 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -42,7 +42,7 @@ smm-$(CONFIG_SPI_FLASH_SMM) += ../common/spi.c ramstage-y += smi.c smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/finalize.c ../bd82x6x/pch.c
-romstage-y += ../bd82x6x/early_usb.c early_smbus.c ../bd82x6x/early_me.c ../bd82x6x/me_status.c ../bd82x6x/gpio.c early_thermal.c +romstage-y += ../bd82x6x/early_usb.c early_smbus.c ../bd82x6x/early_me.c ../bd82x6x/me_status.c ../common/gpio.c early_thermal.c romstage-y += ../bd82x6x/reset.c romstage-y += ../bd82x6x/early_rcba.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) += ../bd82x6x/early_spi.c diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 0572143..07127fa 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -432,22 +432,6 @@ void southbridge_configure_default_intmap(void); #define PCH_DISABLE_MEI1 (1 << 1) #define PCH_ENABLE_DBDF (1 << 0)
-/* ICH7 GPIOBASE */ -#define GPIO_USE_SEL 0x00 -#define GP_IO_SEL 0x04 -#define GP_LVL 0x0c -#define GPO_BLINK 0x18 -#define GPI_INV 0x2c -#define GPIO_USE_SEL2 0x30 -#define GP_IO_SEL2 0x34 -#define GP_LVL2 0x38 -#define GPIO_USE_SEL3 0x40 -#define GP_IO_SEL3 0x44 -#define GP_LVL3 0x48 -#define GP_RST_SEL1 0x60 -#define GP_RST_SEL2 0x64 -#define GP_RST_SEL3 0x68 - /* ICH7 PMBASE */ #define PM1_STS 0x00 #define WAK_STS (1 << 15) diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index fb96930..319f994 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -32,6 +32,7 @@ * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind */ #include "northbridge/intel/nehalem/nehalem.h" +#include <southbridge/intel/common/gpio.h> #include <arch/pci_mmio_cfg.h>
/* While we read PMBASE dynamically in case it changed, let's diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index 203aeb5..e36b1b2 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -51,10 +51,6 @@ ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) romstage-y += lp_gpio.c ramstage-y += lp_gpio.c smm-$(CONFIG_HAVE_SMI_HANDLER) += lp_gpio.c -else -romstage-y += gpio.c -ramstage-y += gpio.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += gpio.c endif
endif diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 9802284..0e4fa3d 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -27,7 +27,7 @@ #if CONFIG_INTEL_LYNXPOINT_LP #include "lp_gpio.h" #else -#include "gpio.h" +#include "southbridge/intel/common/gpio.h" #endif
const struct rcba_config_instruction pch_early_config[] = { diff --git a/src/southbridge/intel/lynxpoint/gpio.c b/src/southbridge/intel/lynxpoint/gpio.c deleted file mode 100644 index bcf3b76..0000000 --- a/src/southbridge/intel/lynxpoint/gpio.c +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <arch/io.h> -#include <device/device.h> -#include <device/pci.h> -#include "pch.h" -#include "gpio.h" - -#define MAX_GPIO_NUMBER 75 /* zero based */ - -static u16 get_gpio_base(void) -{ -#if defined(__PRE_RAM__) || defined(__SMM__) - return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; -#else - return pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), - GPIO_BASE) & 0xfffc; -#endif -} - -void setup_pch_gpios(const struct pch_gpio_map *gpio) -{ - u16 gpiobase = get_gpio_base(); - - /* GPIO Set 1 */ - if (gpio->set1.level) - outl(*((u32*)gpio->set1.level), gpiobase + GP_LVL); - if (gpio->set1.mode) - outl(*((u32*)gpio->set1.mode), gpiobase + GPIO_USE_SEL); - if (gpio->set1.direction) - outl(*((u32*)gpio->set1.direction), gpiobase + GP_IO_SEL); - if (gpio->set1.reset) - outl(*((u32*)gpio->set1.reset), gpiobase + GP_RST_SEL1); - if (gpio->set1.invert) - outl(*((u32*)gpio->set1.invert), gpiobase + GPI_INV); - if (gpio->set1.blink) - outl(*((u32*)gpio->set1.blink), gpiobase + GPO_BLINK); - - /* GPIO Set 2 */ - if (gpio->set2.level) - outl(*((u32*)gpio->set2.level), gpiobase + GP_LVL2); - if (gpio->set2.mode) - outl(*((u32*)gpio->set2.mode), gpiobase + GPIO_USE_SEL2); - if (gpio->set2.direction) - outl(*((u32*)gpio->set2.direction), gpiobase + GP_IO_SEL2); - if (gpio->set2.reset) - outl(*((u32*)gpio->set2.reset), gpiobase + GP_RST_SEL2); - - /* GPIO Set 3 */ - if (gpio->set3.level) - outl(*((u32*)gpio->set3.level), gpiobase + GP_LVL3); - if (gpio->set3.mode) - outl(*((u32*)gpio->set3.mode), gpiobase + GPIO_USE_SEL3); - if (gpio->set3.direction) - outl(*((u32*)gpio->set3.direction), gpiobase + GP_IO_SEL3); - if (gpio->set3.reset) - outl(*((u32*)gpio->set3.reset), gpiobase + GP_RST_SEL3); -} - -int get_gpio(int gpio_num) -{ - static const int gpio_reg_offsets[] = {0xc, 0x38, 0x48}; - u16 gpio_base = get_gpio_base(); - int index, bit; - - if (gpio_num > MAX_GPIO_NUMBER) - return 0; /* Just ignore wrong gpio numbers. */ - - index = gpio_num / 32; - bit = gpio_num % 32; - - return (inl(gpio_base + gpio_reg_offsets[index]) >> bit) & 1; -} - -/* - * get a number comprised of multiple GPIO values. gpio_num_array points to - * the array of gpio pin numbers to scan, terminated by -1. - */ -unsigned get_gpios(const int *gpio_num_array) -{ - int gpio; - unsigned bitmask = 1; - unsigned vector = 0; - - while (bitmask && - ((gpio = *gpio_num_array++) != -1)) { - if (get_gpio(gpio)) - vector |= bitmask; - bitmask <<= 1; - } - return vector; -} - -void set_gpio(int gpio_num, int value) -{ - static const int gpio_reg_offsets[] = {0xc, 0x38, 0x48}; - u16 gpio_base = get_gpio_base(); - int index, bit; - u32 config; - - if (gpio_num > MAX_GPIO_NUMBER) - return; /* Just ignore wrong gpio numbers. */ - - index = gpio_num / 32; - bit = gpio_num % 32; - - config = inl(gpio_base + gpio_reg_offsets[index]); - config &= ~(1 << bit); - config |= value << bit; - outl(config, gpio_base + gpio_reg_offsets[index]); -} - -int gpio_is_native(int gpio_num) -{ - static const int gpio_reg_offsets[] = { - GPIO_USE_SEL, GPIO_USE_SEL2, GPIO_USE_SEL3 - }; - u16 gpio_base = get_gpio_base(); - int index, bit; - u32 config; - - if (gpio_num > MAX_GPIO_NUMBER) - return 0; /* Just ignore wrong gpio numbers. */ - - index = gpio_num / 32; - bit = gpio_num % 32; - - config = inl(gpio_base + gpio_reg_offsets[index]); - return !(config & (1 << bit)); -} diff --git a/src/southbridge/intel/lynxpoint/gpio.h b/src/southbridge/intel/lynxpoint/gpio.h deleted file mode 100644 index 5f62a65..0000000 --- a/src/southbridge/intel/lynxpoint/gpio.h +++ /dev/null @@ -1,165 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef INTEL_LYNXPOINT_GPIO_H -#define INTEL_LYNXPOINT_GPIO_H - -/* ICH7 GPIOBASE */ -#define GPIO_USE_SEL 0x00 -#define GP_IO_SEL 0x04 -#define GP_LVL 0x0c -#define GPO_BLINK 0x18 -#define GPI_INV 0x2c -#define GPIO_USE_SEL2 0x30 -#define GP_IO_SEL2 0x34 -#define GP_LVL2 0x38 -#define GPIO_USE_SEL3 0x40 -#define GP_IO_SEL3 0x44 -#define GP_LVL3 0x48 -#define GP_RST_SEL1 0x60 -#define GP_RST_SEL2 0x64 -#define GP_RST_SEL3 0x68 - -#define GPIO_MODE_NATIVE 0 -#define GPIO_MODE_GPIO 1 -#define GPIO_MODE_NONE 1 - -#define GPIO_DIR_OUTPUT 0 -#define GPIO_DIR_INPUT 1 - -#define GPIO_NO_INVERT 0 -#define GPIO_INVERT 1 - -#define GPIO_LEVEL_LOW 0 -#define GPIO_LEVEL_HIGH 1 - -#define GPIO_NO_BLINK 0 -#define GPIO_BLINK 1 - -#define GPIO_RESET_PWROK 0 -#define GPIO_RESET_RSMRST 1 - -struct pch_gpio_set1 { - u32 gpio0 : 1; - u32 gpio1 : 1; - u32 gpio2 : 1; - u32 gpio3 : 1; - u32 gpio4 : 1; - u32 gpio5 : 1; - u32 gpio6 : 1; - u32 gpio7 : 1; - u32 gpio8 : 1; - u32 gpio9 : 1; - u32 gpio10 : 1; - u32 gpio11 : 1; - u32 gpio12 : 1; - u32 gpio13 : 1; - u32 gpio14 : 1; - u32 gpio15 : 1; - u32 gpio16 : 1; - u32 gpio17 : 1; - u32 gpio18 : 1; - u32 gpio19 : 1; - u32 gpio20 : 1; - u32 gpio21 : 1; - u32 gpio22 : 1; - u32 gpio23 : 1; - u32 gpio24 : 1; - u32 gpio25 : 1; - u32 gpio26 : 1; - u32 gpio27 : 1; - u32 gpio28 : 1; - u32 gpio29 : 1; - u32 gpio30 : 1; - u32 gpio31 : 1; -} __attribute__ ((packed)); - -struct pch_gpio_set2 { - u32 gpio32 : 1; - u32 gpio33 : 1; - u32 gpio34 : 1; - u32 gpio35 : 1; - u32 gpio36 : 1; - u32 gpio37 : 1; - u32 gpio38 : 1; - u32 gpio39 : 1; - u32 gpio40 : 1; - u32 gpio41 : 1; - u32 gpio42 : 1; - u32 gpio43 : 1; - u32 gpio44 : 1; - u32 gpio45 : 1; - u32 gpio46 : 1; - u32 gpio47 : 1; - u32 gpio48 : 1; - u32 gpio49 : 1; - u32 gpio50 : 1; - u32 gpio51 : 1; - u32 gpio52 : 1; - u32 gpio53 : 1; - u32 gpio54 : 1; - u32 gpio55 : 1; - u32 gpio56 : 1; - u32 gpio57 : 1; - u32 gpio58 : 1; - u32 gpio59 : 1; - u32 gpio60 : 1; - u32 gpio61 : 1; - u32 gpio62 : 1; - u32 gpio63 : 1; -} __attribute__ ((packed)); - -struct pch_gpio_set3 { - u32 gpio64 : 1; - u32 gpio65 : 1; - u32 gpio66 : 1; - u32 gpio67 : 1; - u32 gpio68 : 1; - u32 gpio69 : 1; - u32 gpio70 : 1; - u32 gpio71 : 1; - u32 gpio72 : 1; - u32 gpio73 : 1; - u32 gpio74 : 1; - u32 gpio75 : 1; -} __attribute__ ((packed)); - -struct pch_gpio_map { - struct { - const struct pch_gpio_set1 *mode; - const struct pch_gpio_set1 *direction; - const struct pch_gpio_set1 *level; - const struct pch_gpio_set1 *reset; - const struct pch_gpio_set1 *invert; - const struct pch_gpio_set1 *blink; - } set1; - struct { - const struct pch_gpio_set2 *mode; - const struct pch_gpio_set2 *direction; - const struct pch_gpio_set2 *level; - const struct pch_gpio_set2 *reset; - } set2; - struct { - const struct pch_gpio_set3 *mode; - const struct pch_gpio_set3 *direction; - const struct pch_gpio_set3 *level; - const struct pch_gpio_set3 *reset; - } set3; -}; - -/* Configure GPIOs with mainboard provided settings */ -void setup_pch_gpios(const struct pch_gpio_map *gpio); - -#endif diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h index 4db6113..c35e770 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.h +++ b/src/southbridge/intel/lynxpoint/lp_gpio.h @@ -163,4 +163,15 @@ struct pch_lp_gpio_map { /* Configure GPIOs with mainboard provided settings */ void setup_pch_lp_gpios(const struct pch_lp_gpio_map map[]);
+/* get GPIO pin value */ +int get_gpio(int gpio_num); +/* + * get a number comprised of multiple GPIO values. gpio_num_array points to + * the array of gpio pin numbers to scan, terminated by -1. + */ +unsigned get_gpios(const int *gpio_num_array); + +void set_gpio(int gpio_num, int value); + +int gpio_is_native(int gpio_num); #endif diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 46c3f63..2b834ff 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -167,21 +167,6 @@ void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4); void disable_all_gpe(void); void enable_gpe(u32 mask); void disable_gpe(u32 mask); -/* - * get GPIO pin value - */ -int get_gpio(int gpio_num); -/* - * Get a number comprised of multiple GPIO values. gpio_num_array points to - * the array of gpio pin numbers to scan, terminated by -1. - */ -unsigned get_gpios(const int *gpio_num_array); -/* - * Set GPIO pin value. - */ -void set_gpio(int gpio_num, int value); -/* Return non-zero if gpio is set to native function. 0 otherwise. */ -int gpio_is_native(int gpio_num);
#if !defined(__PRE_RAM__) && !defined(__SMM__) #include <device/device.h> diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 41e8890..ea0d312 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -20,6 +20,7 @@ #include <device/pciexp.h> #include <device/pci_ids.h> #include "pch.h" +#include "southbridge/intel/common/gpio.h"
static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or); static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or);