Attention is currently required from: Angel Pons, Keith Hui, Nicholas Chin.
Bill XIE has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email )
Change subject: mb/asus/p8z77-v: Add support to reconfigure PCIe lanes ......................................................................
Patch Set 8:
(1 comment)
File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c:
https://review.coreboot.org/c/coreboot/+/85413/comment/9e3601bb_9d537262?usp... : PS7, Line 104: 0x40
So efivarfs does prepend the 4-byte attributes to EFI variables. […]
When PCIEPCS1 == 0, PCIEX1_2 remains not working with X_QSW_SEL2,3,4 being 111 and the following log:
[DEBUG] PCI: 00:00:1c.3 scanning...
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 06 [INFO ] POST: 0x24 [INFO ] POST: 0x25 [INFO ] PCI: 00:00:1c.3: Setting Max_Payload_Size to 128 for devices under this root port [WARN ] PCI: 00:00:1c.3: Has a slow downstream device. Enumeration failed. [DEBUG] scan_bus: bus PCI: 00:00:1c.3 finished in 26 msecs