Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41807 )
Change subject: mb/google/dedede: Enable Heci1 device ......................................................................
mb/google/dedede: Enable Heci1 device
Enable heci1 device from devicetree for PCI enumeration. This is required for ME status dump using HFSTSx resgisters in PCI config space. Heci1 device is later disabled through heci disable flow.
TEST=Build, boot waddledoo. ME status dump is seen in console logs. Signed-off-by: Aamir Bohra aamir.bohra@intel.com
Change-Id: Icb77db3f0666c2d14ebef2c3214564346d1fd3c9 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/41807/1
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index c891e6e..6509f19 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -255,7 +255,7 @@ device pci 15.1 on end # I2C 1 device pci 15.2 on end # I2C 2 device pci 15.3 on end # I2C 3 - device pci 16.0 off end # HECI 1 + device pci 16.0 on end # HECI 1 device pci 16.1 off end # HECI 2 device pci 16.4 off end # HECI 3 device pci 16.5 off end # HECI 4