Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54389 )
Change subject: mb/asus/h61m-cs: Switch to overridetree setup ......................................................................
mb/asus/h61m-cs: Switch to overridetree setup
Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus H61M-CS remains identical when not adding the .config file in it.
Change-Id: I34eb5387fddcb3505c9218b20b706b773e979b0e Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/asus/h61-series/Kconfig R src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb 2 files changed, 4 insertions(+), 31 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/54389/1
diff --git a/src/mainboard/asus/h61-series/Kconfig b/src/mainboard/asus/h61-series/Kconfig index 8b3f04d..06c4a57 100644 --- a/src/mainboard/asus/h61-series/Kconfig +++ b/src/mainboard/asus/h61-series/Kconfig @@ -32,14 +32,14 @@ default "P8H61-M PRO" if BOARD_ASUS_P8H61_M_PRO
# TODO: remove once all boards use overridetrees -if BOARD_ASUS_P8H61_M_LX3_R2_0 || BOARD_ASUS_P8H61_M_PRO +if !BOARD_ASUS_P8H61_M_LX
config OVERRIDE_DEVICETREE string default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
endif -if !BOARD_ASUS_P8H61_M_LX3_R2_0 && !BOARD_ASUS_P8H61_M_PRO +if BOARD_ASUS_P8H61_M_LX
config DEVICETREE string diff --git a/src/mainboard/asus/h61-series/variants/h61m-cs/devicetree.cb b/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb similarity index 63% rename from src/mainboard/asus/h61-series/variants/h61m-cs/devicetree.cb rename to src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb index 3ec5e5f..89ef419 100644 --- a/src/mainboard/asus/h61-series/variants/h61m-cs/devicetree.cb +++ b/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb @@ -1,32 +1,10 @@ ## SPDX-License-Identifier: GPL-2.0-or-later
chip northbridge/intel/sandybridge - device cpu_cluster 0 on - chip cpu/intel/model_206ax - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - device lapic 0x0 on end - device lapic 0xacac off end - end - end device domain 0 on subsystemid 0x1043 0x844d inherit - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" + chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" - register "sata_port_map" = "0x33" - register "spi_lvscc" = "0x2005" - register "spi_uvscc" = "0x2005" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 device pci 1b.0 on # High Definition Audio Audio controller subsystemid 0x1043 0x8445 end @@ -40,8 +18,7 @@ end device pci 1c.6 off end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge PCI-LPC bridge chip superio/nuvoton/nct6779d device pnp 2e.1 off end # Parallel @@ -78,10 +55,6 @@ device pnp 2e.16 off end # Deep Sleep end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal end end end