[coreboot-gerrit] Change in coreboot[master]: util: Add spd_tools to generate SPDs for TGL boards

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41612 )

Change subject: util: Add spd_tools to generate SPDs for TGL boards
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Patch Set 10:

(1 comment)

https://review.coreboot.org/c/coreboot/+/41612/10/util/spd_tools/intel/lp4x/... 
File util/spd_tools/intel/lp4x/README.md:

https://review.coreboot.org/c/coreboot/+/41612/10/util/spd_tools/intel/lp4x/... 
PS10, Line 65: SDRAM minimum cycle time
> What about SDRAM maximum cycle time?

https://review.coreboot.org/c/coreboot/+/41612/8/util/spd_tools/intel/lp4x/g...

JEDEC spec says that max TCK should be 100ns. I see that all parts follow the same. I was thinking of keeping it as constant especially since we can't really encode 100ns in the SPD byte and instead have to stick to using 0xff i.e. 31.875ns.