[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Update fsp params for Jasper Lake.

[Maulik V Vaghela (Code Review)]

Hello Patrick Rudolph, Karthikeyan Ramasubramanian, Subrata Banik, Aamir Bohra, Rizwan Qureshi, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38461

to look at the new patch set (#3).

Change subject: soc/intel/tigerlake: Update fsp params for Jasper Lake.
......................................................................

soc/intel/tigerlake: Update fsp params for Jasper Lake.

Update fsp parameters for Jasper Lake SoC.
Update fsp parameters for various configuration like Graphics, USB, xDCI,
PCI root ports etc.

These are the initial settings for JSL.

BUG=None
BRANCH=None
TEST=Compilation for jasper lake board is working

Change-Id: Ia8e88f92989fe40d7bd1c28947e005cc0d862fcb
Signed-off-by: Maulik V Vaghela 
---
M src/soc/intel/tigerlake/fsp_params_jsl.c
M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c
2 files changed, 237 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/38461/3