Harsha B R has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72742 )
Change subject: mb/intel/mtlrvp: Remove GPP_A12 for chrome platform ......................................................................
mb/intel/mtlrvp: Remove GPP_A12 for chrome platform
This patch removes the configuration of GPP_A12 for mtlrvp. Garfield Peak (WLAN) doesn't use GPP_A12 for WAKE_N. Configuring GPP_A12 pin prevents system entering G3 (reboots) on issuing shutdown -h now. Hence configuring GPP_A12 as PAD_NC.
BUG=b:224325352 BRANCH=None TEST=On issuing 'shutdown -h now' system enters G3
Signed-off-by: Harsha B R harsha.b.r@intel.com Change-Id: I5e46b8afd3e0055440fd3c3db4aa5a9f1d4aa556 --- M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/gpio.c 1 file changed, 21 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/72742/1
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/gpio.c b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/gpio.c index 892a950..2c48a0e 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/gpio.c +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/gpio.c @@ -19,8 +19,8 @@ /* GPP_A06 : GPP_A06 ==> ESPI_SOC_RESET_L configured on reset, do not touch */ /* GPP_A11: PEG_SLOT_DGPU_SEL_N */ PAD_CFG_GPO(GPP_A11, 1, DEEP), - /* GPP_A12: WIFI_WAKE_N */ - PAD_CFG_GPI_SCI(GPP_A12, NONE, DEEP, LEVEL, INVERT), + /* GPP_A12: NC */ + PAD_NC(GPP_A12, NONE), /* GPP_A13: M2_SSD2_RST_N */ PAD_CFG_GPO(GPP_A13, 1, DEEP), /* GPP_A14: M2_CPU_SSD4_RESET_N */