[coreboot-gerrit] Change in ...coreboot[master]: mb/google/sarien/variants/sarien: Update dptf.asl for EVT1

[John Su (Code Review)]

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31170

Change subject: mb/google/sarien/variants/sarien: Update dptf.asl for EVT1
......................................................................

mb/google/sarien/variants/sarien: Update dptf.asl for EVT1

Follow thermal table (b:123383634 comment#1) for EVT1 tunning.

BUG=b:123383634
BRANCH=sarien
TEST=Built and tested on sarien system

Change-Id: I22908e4bf39aedb8cf31a9060084f6f36bff56ca
Signed-off-by: John Su 
---
M src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl
1 file changed, 15 insertions(+), 15 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/31170/1

diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl
index d6a1274..66839a0 100644
--- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl
@@ -13,42 +13,42 @@
  * GNU General Public License for more details.
  */

-#define DPTF_CPU_PASSIVE	80
+#define DPTF_CPU_PASSIVE	99
 #define DPTF_CPU_CRITICAL	100

/* Skin Sensor for CPU VR temperature monitor */
 #define DPTF_TSR0_SENSOR_ID	1
 #define DPTF_TSR0_SENSOR_NAME	"Skin"
-#define DPTF_TSR0_PASSIVE	55
-#define DPTF_TSR0_CRITICAL	70
+#define DPTF_TSR0_PASSIVE	71
+#define DPTF_TSR0_CRITICAL	100

/* Memory Sensor for DDR temperature monitor */
 #define DPTF_TSR1_SENSOR_ID	2
 #define DPTF_TSR1_SENSOR_NAME	"DDR"
-#define DPTF_TSR1_PASSIVE	55
-#define DPTF_TSR1_CRITICAL	80
+#define DPTF_TSR1_PASSIVE	56
+#define DPTF_TSR1_CRITICAL	100

/* M.2 Sensor for Ambient temperature monitor */
 #define DPTF_TSR2_SENSOR_ID	3
 #define DPTF_TSR2_SENSOR_NAME	"Ambient"
-#define DPTF_TSR2_PASSIVE	55
-#define DPTF_TSR2_CRITICAL	70
+#define DPTF_TSR2_PASSIVE	90
+#define DPTF_TSR2_CRITICAL	100

#undef DPTF_ENABLE_FAN_CONTROL
 #undef DPTF_ENABLE_CHARGER

Name (DTRT, Package () {
    /* CPU Throttle Effect on CPU */
-	Package () { _SB.PCI0.TCPU, _SB.PCI0.TCPU, 100, 10, 0, 0, 0, 0 },
+	Package () { _SB.PCI0.TCPU, _SB.PCI0.TCPU, 5000, 10, 0, 0, 0, 0 },

/* CPU Throttle Effect on Skin (TSR0)  */
-	Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+	Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR0, 200, 10, 0, 0, 0, 0 },

/* CPU Throttle Effect on DDR (TSR1)  */
-	Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR1, 100, 90, 0, 0, 0, 0 },
+	Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR1, 2000, 10, 0, 0, 0, 0 },

/* CPU Throttle Effect on Ambient (TSR2)  */
-	Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+	Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR2, 200, 10, 0, 0, 0, 0 },
 })

Name (MPPC, Package ()
@@ -58,16 +58,16 @@
    	0,	/* PowerLimitIndex, 0 for Power Limit 1 */
    	3000,	/* PowerLimitMinimum */
    	25000,	/* PowerLimitMaximum */
-		28000,	/* TimeWindowMinimum */
-		32000,	/* TimeWindowMaximum */
+		10000,	/* TimeWindowMinimum */
+		10000,	/* TimeWindowMaximum */
    	100	/* StepSize */
    },
    Package () {	/* Power Limit 2 */
    	1,	/* PowerLimitIndex, 1 for Power Limit 2 */
-		15000,	/* PowerLimitMinimum */
+		3000,	/* PowerLimitMinimum */
    	51000,	/* PowerLimitMaximum */
    	28000,	/* TimeWindowMinimum */
-		32000,	/* TimeWindowMaximum */
+		28000,	/* TimeWindowMaximum */
    	100	/* StepSize */
    }
 })