[coreboot-gerrit] Change in coreboot[master]: soc/intel/jasperlake: Add CdClock frequency config

[Subrata Banik (Code Review)]

Attention is currently required from: Nico Huber, Jamie Chen, Henry Sun, Tim Wawrzynczak, Paul Menzel, Ren Kuo, Simon Yang, Angel Pons, Kane Chen, Patrick Rudolph.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60009 )

Change subject: soc/intel/jasperlake: Add CdClock frequency config
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Patch Set 18:

(1 comment)

File src/soc/intel/jasperlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/60009/comment/dd04c618_39083b5c 
PS17, Line 212: 	params->CdClock = config->cd_clock ? config->cd_clock - 1 : 0xff;
> Updated fsp header in patchset#18, and the inside of fsp related change will release later.

Can you please update commit msg saying you have updated the FSP-S UPD help text to align the code behaviour with the UPD for CdClock.

Hopefully next time someone updating the JSL FSP headers shouldn't override this to default as you are not fixing it at source yet ?