[coreboot-gerrit] Change in coreboot[master]: soc/intel/{jsl,tgl}: Fix GRXS function to get GPIO number proper

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45738 )

Change subject: soc/intel/{jsl,tgl}: Fix GRXS function to get GPIO number proper
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soc/intel/{jsl,tgl}: Fix GRXS function to get GPIO number proper

This patch ensures that GRXS perform PAD_CFG0_RX_STATE mask first
and then right shift PAD_CFG0_RX_STATE_BIT to get correct GPIO number.

Change-Id: I96611936f70f79e9dc5ee9414ec68cef00d0d13a
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45738
Reviewed-by: Furquan Shaikh 
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/jasperlake/acpi/gpio_op.asl
M src/soc/intel/tigerlake/acpi/gpio_op.asl
2 files changed, 2 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Angel Pons: Looks good to me, approved

diff --git a/src/soc/intel/jasperlake/acpi/gpio_op.asl b/src/soc/intel/jasperlake/acpi/gpio_op.asl
index 9b9dc44..ff12da4 100644
--- a/src/soc/intel/jasperlake/acpi/gpio_op.asl
+++ b/src/soc/intel/jasperlake/acpi/gpio_op.asl
@@ -11,7 +11,7 @@
    {
    	VAL0, 32
    }
-	Local0 = PAD_CFG0_RX_STATE & (VAL0 >> PAD_CFG0_RX_STATE_BIT)
+	Local0 = (PAD_CFG0_RX_STATE & VAL0) >> PAD_CFG0_RX_STATE_BIT

Return (Local0)
 }
diff --git a/src/soc/intel/tigerlake/acpi/gpio_op.asl b/src/soc/intel/tigerlake/acpi/gpio_op.asl
index 9b9dc44..ff12da4 100644
--- a/src/soc/intel/tigerlake/acpi/gpio_op.asl
+++ b/src/soc/intel/tigerlake/acpi/gpio_op.asl
@@ -11,7 +11,7 @@
    {
    	VAL0, 32
    }
-	Local0 = PAD_CFG0_RX_STATE & (VAL0 >> PAD_CFG0_RX_STATE_BIT)
+	Local0 = (PAD_CFG0_RX_STATE & VAL0) >> PAD_CFG0_RX_STATE_BIT

Return (Local0)
 }