Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40722 )
Change subject: [WIP] Add Multiple Segment support ......................................................................
Patch Set 3:
(3 comments)
Sorry for the delay, it was a busy week.
Looks good overall. I'm not 100% sure about the resources reported in _CRS. The spec says PCI segment groups are a mere software features that shouldn't affect the hardware. And in hardware there can't be a second device that would positively decode the same resources anyway. I'm not sure if we have to report these resource again. Maybe we don't need the `extrahostbridge.asl`?
I think we can do the Kconfig and what it entails first, and the ACPI changes in a separate commit.
https://review.coreboot.org/c/coreboot/+/40722/3/src/soc/intel/common/block/... File src/soc/intel/common/block/include/intelblocks/systemagent.h:
https://review.coreboot.org/c/coreboot/+/40722/3/src/soc/intel/common/block/... PS3, Line 13: x Maybe give this a name for clarity, e.g. `segments`.
Alternatively, as we seem to pass always the same value anyway:
#define PCIEXBAR_LENGTH_MIB (CONFIG_PCI_SEGMENT_GROUPS * 256 * MiB)
https://review.coreboot.org/c/coreboot/+/40722/3/src/soc/intel/common/block/... File src/soc/intel/common/block/systemagent/Kconfig:
https://review.coreboot.org/c/coreboot/+/40722/3/src/soc/intel/common/block/... PS3, Line 12: config SA_PCI_SEGMENT_GROUPS This is not Intel specific, IMO it belongs into src/device/Kconfig. Without the SA_ prefix ofc.
Only the `default 2 if TCSS_PCIE_SEGMENT` should be given here.
https://review.coreboot.org/c/coreboot/+/40722/3/src/soc/intel/common/block/... PS3, Line 13: hex Can be `int`.