[coreboot-gerrit] Change in coreboot[master]: sb/intel/bd82x6x: Split `pch_iobp_update` function

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49179 )

Change subject: sb/intel/bd82x6x: Split `pch_iobp_update` function
......................................................................

sb/intel/bd82x6x: Split `pch_iobp_update` function

A follow-up needs to use the value of an IOBP register in a condition,
so split the read and write operations into independent functions.

Change-Id: Ic8fe5be8f0cf8e4672d3e32db7746609ff5da841
Signed-off-by: Angel Pons 
---
M src/southbridge/intel/bd82x6x/common.c
M src/southbridge/intel/bd82x6x/pch.h
2 files changed, 23 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/49179/1

diff --git a/src/southbridge/intel/bd82x6x/common.c b/src/southbridge/intel/bd82x6x/common.c
index 3fad12e..bd1b4cd 100644
--- a/src/southbridge/intel/bd82x6x/common.c
+++ b/src/southbridge/intel/bd82x6x/common.c
@@ -73,7 +73,7 @@
    return 0;
 }

-void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
+u32 pch_iobp_read(u32 address)
 {
    u32 data;

@@ -85,24 +85,26 @@
    	RCBA32(IOBPS) = IOBPS_RW_BX;
    else
    	RCBA32(IOBPS) = IOBPS_READ_AX;
+
    if (!iobp_poll())
-		return;
+		return 0;

/* Read IOBP data */
    data = RCBA32(IOBPD);
    if (!iobp_poll())
-		return;
+		return 0;

/* Check for successful transaction */
    if ((RCBA32(IOBPS) & 0x6) != 0) {
    	printk(BIOS_ERR, "IOBP read 0x%08x failed\n", address);
-		return;
+		return 0;
    }

-	/* Update the data */
-	data &= andvalue;
-	data |= orvalue;
+	return data;
+}

+void pch_iobp_write(u32 address, u32 data)
+{
    /* WRITE OPCODE */
    if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
    	RCBA32(IOBPS) = IOBPS_RW_BX;
@@ -116,3 +118,14 @@
    if (!iobp_poll())
    	return;
 }
+
+void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
+{
+	u32 data = pch_iobp_read(address);
+
+	/* Update the data */
+	data &= andvalue;
+	data |= orvalue;
+
+	pch_iobp_write(address, data);
+}
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 3b91e31..42c56a2 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -43,6 +43,9 @@
 int pch_silicon_revision(void);
 int pch_silicon_type(void);
 int pch_silicon_supported(int type, int rev);
+
+u32 pch_iobp_read(u32 address);
+void pch_iobp_write(u32 address, u32 data);
 void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);

void enable_usb_bar(void);