[coreboot-gerrit] Change in coreboot[master]: vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header file for Tiger Lake

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39117 )

Change subject: vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header file for Tiger Lake
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Patch Set 2:

(2 comments)

https://review.coreboot.org/c/coreboot/+/39117/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39117/2//COMMIT_MSG@10 
PS2, Line 10: Added
Add

https://review.coreboot.org/c/coreboot/+/39117/2//COMMIT_MSG@10 
PS2, Line 10: Added SerialIoUartAutoFlow, Enable8254ClockGating, Enable8254ClockGatingOnS3 UPD
Please add a blank line above.